Pinned Loading

1. Integrated_circuit_design_LATEX_report Integrated_circuit_design_LATEX_report Public

2. Undergraduate_thesis Undergraduate_thesis Public

3. cannyedge-HLS cannyedge-HLS Public

   canny edge HLS implementation

   LLVM 1

4. compArch-vhdl-sysVeri-cocotb compArch-vhdl-sysVeri-cocotb Public

   VHDL

5. computerArch-bits-assignment computerArch-bits-assignment Public

   single cycle implementation

   Verilog

6. sobel-filter-implementation-on-zedboard sobel-filter-implementation-on-zedboard Public

   implementation files for zed board , can be used for other image processing IP generated by HLS

   VHDL 1 1