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Vinay Dabholkar

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1990 – 1999

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1998
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Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1325-1333 (1998)
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Vinay Dabholkar, Sreejit Chakravarty:
Computing Stress Tests for Gate Oxide Shorts. VLSI Design 1998: 378-391
1997
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Vinay Dabholkar, Sreejit Chakravarty:
Computing stress tests for interconnect defects. Asian Test Symposium 1997: 143-148
1995
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Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Janak H. Patel:
Cyclic stress tests for full scan circuits. VTS 1995: 89-94

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Vinay Dabholkar

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1990 – 1999

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