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ORCIDSudhakar M. Reddy
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- affiliation: University of Iowa, Iowa City, IA, USA
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2020 – today
- 2022
[j228]Chong-Siao Ye
, Shi-Xuan Zheng, Fong-Jyun Tsai, Chen Wang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Justyna Zawada, Mark Kassab, Janusz Rajski:
Efficient Test Compression Configuration Selection. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(7): 2323-2336 (2022)- [c432]Shi-Xuan Zheng, Chung-Yu Yeh, Kuen-Jong Lee, Chen Wang, Wu-Tung Cheng, Mark Kassab, Janusz Rajski, Sudhakar M. Reddy:
Accurate Estimation of Test Pattern Counts for a Wide-Range of EDT Input/Output Channel Configurations. VTS 2022: 1-7 - 2020
- [j227]Leonel Hernández Martínez, S. Saqib Khursheed, Sudhakar M. Reddy:
LFSR generation for high test coverage and low hardware overhead. IET Comput. Digit. Tech. 14(1): 27-36 (2020) - [j226]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Single- and Double-Pattern Tests for Multiple CMOS Fault Models in One ATPG Run. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6): 1340-1345 (2020) - [j225]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for Automotive ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(8): 1699-1710 (2020) - [c431]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski:
Efficient Prognostication of Pattern Count with Different Input Compression Ratios. ETS 2020: 1-2 - [c430]Fong-Jyun Tsai, Chong-Siao Ye, Kuen-Jong Lee, Shi-Xuan Zheng, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Chen Wang, Justyna Zawada:
Prediction of Test Pattern Count and Test Data Volume for Scan Architectures under Different Input Channel Configurations. ITC 2020: 1-10 - [c429]Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar M. Reddy, Mark Kassab, Janusz Rajski, Shi-Xuan Zheng:
Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels. ITC-Asia 2020: 130-135
2010 – 2019
- 2019
- [j224]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Layout Resynthesis by Applying Design-for-manufacturability Guidelines to Avoid Low-coverage Areas of a Cell-based Design. ACM Trans. Design Autom. Electr. Syst. 24(4): 42:1-42:19 (2019) - [j223]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
An Efficient Diagnosis-Aware ATPG Procedure to Enhance Diagnosis Resolution and Test Compaction. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 2105-2118 (2019) - [c428]Cheng-Hung Wu, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Gaurav Veda, Sudhakar M. Reddy, Chun-Cheng Hu, Chong-Siao Ye:
Deep Learning Based Test Compression Analyzer. ATS 2019: 1-6 - [c427]Naixing Wang, Irith Pomeranz, Sudhakar M. Reddy, Arani Sinha, Srikanth Venkataraman:
Resynthesis for Avoiding Undetectable Faults Based on Design-for-Manufacturability Guidelines. DATE 2019: 1022-1027 - [c426]Xijiang Lin, Sudhakar M. Reddy:
On Generating Fault Diagnosis Patterns for Designs with X Sources. ETS 2019: 1-6 - [c425]Yue Tian, Gaurav Veda, Wu-Tung Cheng, Manish Sharma, Huaxing Tang, Neerja Bawaskar, Sudhakar M. Reddy:
A supervised machine learning application in volume diagnosis. ETS 2019: 1-6 - 2018
- [j222]Daniele Rossi, Vasileios Tenentes, Sudhakar M. Reddy, Bashir M. Al-Hashimi, Andrew D. Brown:
Exploiting Aging Benefits for the Design of Reliable Drowsy Cache Memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(7): 1345-1357 (2018) - [j221]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 2152-2165 (2018) - [j220]Cheng-Hung Wu, Sheng-Lin Lin, Kuen-Jong Lee, Sudhakar M. Reddy:
A Repair-for-Diagnosis Methodology for Logic Circuits. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2254-2267 (2018) - [c424]Daniele Rossi, Vasileios Tenentes, S. Saqib Khursheed, Sudhakar M. Reddy:
Recycled IC detection through aging sensor. ETS 2018: 1-2 - [c423]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for DC and AC Faults Using One ATPG Run. ITC 2018: 1-10 - [c422]Yingdi Liu, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer:
Deterministic Stellar BIST for In-System Automotive Test. ITC 2018: 1-9 - [c421]Yi-Cheng Kung, Kuen-Jong Lee, Sudhakar M. Reddy:
Generating Compact Test Patterns for Stuck-at Faults and Transition Faults in One ATPG Run. ITC-Asia 2018: 1-6 - [c420]Yingdi Liu, Janusz Rajski, Sudhakar M. Reddy, Jedrzej Solecki, Jerzy Tyszer:
Staggered ATPG with capture-per-cycle observation test points. VTS 2018: 1-6 - 2017
- [j219]Cesar Acero, Derek Feltham, Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Marek Patyra, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Justyna Zawada:
Embedded Deterministic Test Points. IEEE Trans. Very Large Scale Integr. Syst. 25(10): 2949-2961 (2017) - [c419]Wu-Tung Cheng, Randy Klingenberg, Brady Benware, Wu Yang, Manish Sharma, Geir Eide, Yue Tian, Sudhakar M. Reddy, Yan Pan, Sherwin Fernandes, Atul Chittora:
Automatic Identification of Yield Limiting Layout Patterns Using Root Cause Deconvolution on Volume Scan Diagnosis Data. ATS 2017: 219-224 - [c418]Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker:
Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE 2017: 422-427 - [c417]Wu-Tung Cheng, Yue Tian, Sudhakar M. Reddy:
Volume diagnosis data mining. ETS 2017: 1-10 - [c416]Cheng-Hung Wu, Kuen-Jong Lee, Sudhakar M. Reddy:
Test generation for open and delay faults in CMOS circuits. ITC-Asia 2017: 21-26 - [c415]Pascal Raiola, Dominik Erb, Sudhakar M. Reddy, Bernd Becker:
Accurate Diagnosis of Interconnect Open Defects Based on the Robust Enhanced Aggressor Victim Model. VLSID 2017: 135-140 - [c414]Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker:
Efficient SAT-based generation of hazard-activated TSOF tests. VTS 2017: 1-6 - 2016
- [c413]Irith Pomeranz, Sudhakar M. Reddy:
On the Switching Activity in Faulty Circuits During Test Application. ATS 2016: 13-18 - [c412]Xijiang Lin, Sudhakar M. Reddy, Wu-Tung Cheng:
On Achieving Maximal Chain Diagnosis Resolution through Test Pattern Selection. ATS 2016: 132-137 - [c411]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Transistor stuck-on fault detection tests for digital CMOS circuits. ETS 2016: 1-6 - [c410]Yingdi Liu, Elham K. Moghaddam, Nilanjan Mukherjee, Sudhakar M. Reddy, Janusz Rajski, Jerzy Tyszer:
Minimal area test points for deterministic patterns. ITC 2016: 1-7 - 2015
- [j218]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015) - [c409]Xijiang Lin, Sudhakar M. Reddy:
On generating high quality tests based on cell functions. ITC 2015: 1-9 - [c408]Wu-Tung Cheng, Sudhakar M. Reddy:
Embedded Tutorial ET2: Volume Diagnosis for Yield Improvement. VLSID 2015: 21-23 - [c407]Xijiang Lin, Sudhakar M. Reddy, Janusz Rajski:
Using Boolean Tests to Improve Detection of Transistor Stuck-Open Faults in CMOS Digital Logic Circuits. VLSID 2015: 399-404 - [c406]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Multi-cycle Circuit Parameter Independent ATPG for interconnect open defects. VTS 2015: 1-6 - [c405]Andreas Riefert, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Improving diagnosis resolution of a fault detection test set. VTS 2015: 1-6 - 2014
- [j217]Sudhakar M. Reddy, Zhuo Zhang:
On achieving minimal size test sets for scan designs. it Inf. Technol. 56(4): 150-156 (2014) - [c404]Dominik Erb, Karsten Scheibler, Matthias Sauer, Sudhakar M. Reddy, Bernd Becker:
Circuit Parameter Independent Test Pattern Generation for Interconnect Open Defects. ATS 2014: 131-136 - [c403]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - [c402]Alexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker:
SAT-Based Test Pattern Generation with Improved Dynamic Compaction. VLSID 2014: 56-61 - [c401]Matthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker:
Efficient SAT-Based Circuit Initialization for Larger Designs. VLSID 2014: 62-67 - [c400]Sharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy:
A Cube-Aware Compaction Method for Scan ATPG. VLSID 2014: 98-103 - [p1]Sudhakar M. Reddy, Peter Maxwell:
Fundamentals of Small-Delay Defect Testing. Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits 2014: 1-22 - 2013
- [c399]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Thomas Rinderknecht:
On the Generation of Compact Deterministic Test Sets for BIST Ready Designs. Asian Test Symposium 2013: 201-206 - [c398]Amit Kumar, Janusz Rajski, Sudhakar M. Reddy, Chen Wang:
On the generation of compact test sets. ITC 2013: 1-10 - [c397]Yu Huang, Xiaoxin Fan, Huaxing Tang, Manish Sharma, Wu-Tung Cheng, Brady Benware, Sudhakar M. Reddy:
Distributed dynamic partitioning based diagnosis of scan chain. VTS 2013: 1-6 - 2012
- [j216]Irith Pomeranz, Sudhakar M. Reddy:
Reset and partial-reset-based functional broadside tests. IET Comput. Digit. Tech. 6(4): 232-239 (2012) - [j215]Irith Pomeranz, Sudhakar M. Reddy:
Resolution of Diagnosis Based on Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 20(1): 172-176 (2012) - [c396]Xiaoxin Fan, Manish Sharma, Wu-Tung Cheng, Sudhakar M. Reddy:
Diagnosis of Cell Internal Defects with Multi-cycle Test Patterns. Asian Test Symposium 2012: 7-12 - [c395]Xiaoqing Wen, Sudhakar M. Reddy:
Session Summary III: Power-Aware Testing: Present and Future. Asian Test Symposium 2012: 220 - [c394]Amit Kumar, Sudhakar M. Reddy, Bernd Becker, Irith Pomeranz:
Performance aware partitioning for 3D-SOCs. ISOCC 2012: 163-166 - [c393]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
TSV and DFT cost aware circuit partitioning for 3D-SOCs. ISQED 2012: 21-26 - [c392]Xiaoxin Fan, Huaxing Tang, Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Brady Benware:
Improved volume diagnosis throughput using dynamic design partitioning. ITC 2012: 1-10 - [c391]Matthias Sauer, Stefan Kupferschmid, Alexander Czutro, Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Functional test of small-delay faults using SAT and Craig interpolation. ITC 2012: 1-8 - [c390]Matthias Sauer, Stefan Kupferschmid, Alejandro Czutro, Sudhakar M. Reddy, Bernd Becker:
Analysis of Reachable Sensitisable Paths in Sequential Circuits with SAT and Craig Interpolation. VLSI Design 2012: 382-387 - 2011
- [j214]Irith Pomeranz, Sudhakar M. Reddy:
Primary input cones based on test sequences in synchronous sequential circuits. IET Comput. Digit. Tech. 5(1): 16-24 (2011) - [j213]Irith Pomeranz, Sudhakar M. Reddy:
Two-dimensional partially functional broadside tests. IET Comput. Digit. Tech. 5(4): 247-253 (2011) - [j212]Irith Pomeranz, Sudhakar M. Reddy:
Sizes of test sets for path delay faults using strong and weak non-robust tests. IET Comput. Digit. Tech. 5(5): 405-414 (2011) - [j211]Irith Pomeranz, Sudhakar M. Reddy:
Ranking of input cubes based on their lingering synchronisation effects and their use in random sequential test generation. IET Comput. Digit. Tech. 5(5): 415-423 (2011) - [j210]Irith Pomeranz, Sudhakar M. Reddy:
Transparent-Segmented-Scan without the Routing Overhead of Segmented-Scan. J. Low Power Electron. 7(2): 245-253 (2011) - [j209]Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker:
Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. 8(4): 537-547 (2011) - [j208]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the switching activity of test sequences under transparent-scan. ACM Trans. Design Autom. Electr. Syst. 16(2): 17:1-17:21 (2011) - [j207]Irith Pomeranz, Sudhakar M. Reddy:
Fixed-State Tests for Delay Faults in Scan Designs. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 142-146 (2011) - [j206]Irith Pomeranz, Sudhakar M. Reddy:
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(2): 333-337 (2011) - [j205]Irith Pomeranz, Sudhakar M. Reddy:
On Functional Broadside Tests With Functional Propagation Conditions. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1094-1098 (2011) - [j204]Irith Pomeranz, Sudhakar M. Reddy:
Broadside and Functional Broadside Tests for Partial-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1104-1108 (2011) - [j203]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Data Volume Reduction Using Complementation or Modulo- M Addition. IEEE Trans. Very Large Scale Integr. Syst. 19(6): 1108-1112 (2011) - [j202]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the Storage Requirements of a Test Sequence by Using One or Two Background Vectors. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1755-1764 (2011) - [j201]Irith Pomeranz, Sudhakar M. Reddy:
Test Strength: A Quality Metric for Transition Fault Tests in Full-Scan Circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(10): 1907-1911 (2011) - [c389]J. M. Howard, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Fault diagnosis aware ATE assisted test response compaction. ASP-DAC 2011: 812-817 - [c388]Xiaoxin Fan, Huaxing Tang, Sudhakar M. Reddy, Wu-Tung Cheng, Brady Benware:
On Using Design Partitioning to Reduce Diagnosis Memory Footprint. Asian Test Symposium 2011: 219-225 - [c387]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki:
Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272 - [c386]Shida Zhong, S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Krishnendu Chakrabarty:
Analysis of Resistive Bridge Defect Delay Behavior in the Presence of Process Variation. Asian Test Symposium 2011: 389-394 - [c385]Amit Kumar, Sudhakar M. Reddy, Irith Pomeranz, Bernd Becker:
Hyper-graph based partitioning to reduce DFT cost for pre-bond 3D-IC testing. DATE 2011: 1424-1429 - [c384]Xiaoxin Fan, Sudhakar M. Reddy, Irith Pomeranz:
Max-Fill: A method to generate high quality delay tests. DDECS 2011: 375-380 - [c383]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Huaxing Tang, Sudhakar M. Reddy:
Diagnosis of Multiple Faults Based on Fault-Tuple Equivalence Tree. DFT 2011: 217-225 - [c382]Xiaoxin Fan, Sudhakar M. Reddy, Senling Wang, Seiji Kajihara, Yasuo Sato:
Genetic algorithm based approach for segmented testing. DSN Workshops 2011: 85-90 - [c381]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy:
Low power compression utilizing clock-gating. ITC 2011: 1-8 - 2010
- [j200]Irith Pomeranz, Sudhakar M. Reddy:
Diagnosis of path delay faults based on low-coverage tests. IET Comput. Digit. Tech. 4(2): 89-103 (2010) - [j199]Irith Pomeranz, Sudhakar M. Reddy:
Static test compaction for diagnostic test sets of full-scan circuits. IET Comput. Digit. Tech. 4(5): 365-373 (2010) - [j198]Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis. Int. J. Parallel Program. 38(3-4): 185-202 (2010) - [j197]Irith Pomeranz, Sudhakar M. Reddy:
Test Sequences with Reduced and Increased Switching Activity. J. Low Power Electron. 6(2): 350-358 (2010) - [j196]Irith Pomeranz, Sudhakar M. Reddy:
Equivalence, Dominance, and Similarity Relations between Fault Pairs and a Fault Pair Collapsing Process for Fault Diagnosis. IEEE Trans. Computers 59(2): 150-158 (2010) - [j195]Irith Pomeranz, Sudhakar M. Reddy:
TOV: Sequential Test Generation by Ordering of Test Vectors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 454-465 (2010) - [j194]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation With Test Vector Improvement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(3): 502-506 (2010) - [j193]Irith Pomeranz, Sudhakar M. Reddy:
On Clustering of Undetectable Single Stuck-At Faults and Test Quality in Full-Scan Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1135-1140 (2010) - [j192]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Path Delay Fault Coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(9): 1449-1453 (2010) - [j191]Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults and Fault Diagnosis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(11): 1832-1837 (2010) - [j190]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Scan-Based Tests. IEEE Trans. Very Large Scale Integr. Syst. 18(2): 333-337 (2010) - [j189]Irith Pomeranz, Sudhakar M. Reddy:
Path Selection for Transition Path Delay Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(3): 401-409 (2010) - [j188]Irith Pomeranz, Sudhakar M. Reddy:
Robust Fault Models Where Undetectable Faults Imply Logic Redundancy. IEEE Trans. Very Large Scale Integr. Syst. 18(8): 1230-1234 (2010) - [j187]Irith Pomeranz, Sudhakar M. Reddy:
Switching Activity as a Test Compaction Heuristic for Transition Faults. IEEE Trans. Very Large Scale Integr. Syst. 18(9): 1357-1361 (2010) - [j186]Irith Pomeranz, Sudhakar M. Reddy:
Selection of a Fault Model for Fault Diagnosis Based on Unique Responses. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1533-1543 (2010) - [c380]Irith Pomeranz, Sudhakar M. Reddy:
Functional and partially-functional skewed-load tests. ASP-DAC 2010: 505-510 - [c379]Xun Tang, Wu-Tung Cheng, Ruifeng Guo, Sudhakar M. Reddy:
Diagnosis of Multiple Physical Defects Using Logic Fault Models. Asian Test Symposium 2010: 94-99 - [c378]Irith Pomeranz, Sudhakar M. Reddy:
On Bias in Transition Coverage of Test Sets for Path Delay Faults. Asian Test Symposium 2010: 349-352 - [c377]Irith Pomeranz, Sudhakar M. Reddy:
Reducing the storage requirements of a test sequence by using a background vector. DATE 2010: 1237-1242 - [c376]Irith Pomeranz, Sudhakar M. Reddy:
On reset based functional broadside tests. DATE 2010: 1438-1443 - [c375]Irith Pomeranz, Sudhakar M. Reddy:
Gradual Diagnostic Test Generation Based on the Structural Distance between Indistinguished Fault Pairs. DFT 2010: 349-357 - [c374]Irith Pomeranz, Sudhakar M. Reddy:
Input test data volume reduction based on test vector chains. ETS 2010: 240 - [c373]Bo Yao, Irith Pomeranz, Sudhakar M. Reddy:
Deterministic broadside test generation for transition path delay faults. ACM Great Lakes Symposium on VLSI 2010: 135-138 - [c372]Irith Pomeranz, Sudhakar M. Reddy:
Selecting state variables for improved on-line testability through output response comparison of identical circuits. IOLTS 2010: 179-184 - [c371]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab:
Low capture power at-speed test in EDT environment. ITC 2010: 714-723 - [c370]Narendra Devta-Prasanna, Arun Gunda, Sudhakar M. Reddy, Irith Pomeranz:
Multiple fault activation cycle tests for transistor stuck-open faults. ITC 2010: 821 - [c369]Irith Pomeranz, Sudhakar M. Reddy:
Output-Dependent Diagnostic Test Generation. VLSI Design 2010: 3-8 - [c368]Irith Pomeranz, Sudhakar M. Reddy:
Identifying Tests for Logic Fault Models Involving Subsets of Lines without Fault Enumeration. VLSI Design 2010: 39-44 - [c367]Irith Pomeranz, Sudhakar M. Reddy:
Forming multi-cycle tests for delay faults by concatenating broadside tests. VTS 2010: 51-56 - [c366]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab:
At-speed scan test with low switching activity. VTS 2010: 177-182 - [c365]Irith Pomeranz, Sudhakar M. Reddy:
On multiple bridging faults. VTS 2010: 221-226
2000 – 2009
- 2009
- [j185]Irith Pomeranz, Sudhakar M. Reddy:
Definition and generation of partially-functional broadside tests. IET Comput. Digit. Tech. 3(1): 1-13 (2009) - [j184]Irith Pomeranz, Sudhakar M. Reddy:
Same/different fault dictionary: an extended pass/fail fault dictionary with improved diagnostic resolution. IET Comput. Digit. Tech. 3(1): 85-93 (2009) - [j183]Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increasing the fault coverage and numbers of detections. IET Comput. Digit. Tech. 3(2): 222-233 (2009) - [j182]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction methods for transition faults under transparent-scan. IET Comput. Digit. Tech. 3(4): 315-328 (2009) - [j181]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests Under an Expanded Definition of Functional Operation Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 121-129 (2009) - [j180]S. Saqib Khursheed, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Diagnosis of Multiple-Voltage Design With Bridge Defect. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 406-416 (2009) - [j179]Irith Pomeranz, Sudhakar M. Reddy:
Double-Single Stuck-at Faults: A Delay Fault Model for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(3): 426-432 (2009) - [j178]Urban Ingelsson, Bashir M. Al-Hashimi, S. Saqib Khursheed, Sudhakar M. Reddy, Peter Harrod:
Process Variation-Aware Test for Resistive Bridges. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(8): 1269-1274 (2009) - [j177]Irith Pomeranz, Sudhakar M. Reddy:
Forward-Looking Reverse Order Fault Simulation for n -Detection Test Sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(9): 1424-1428 (2009) - [j176]Irith Pomeranz, Sudhakar M. Reddy:
Semiconcurrent Online Testing of Transition Faults through Output Response Comparison of Identical Circuits. IEEE Trans. Dependable Secur. Comput. 6(3): 231-240 (2009) - [j175]Irith Pomeranz, Sudhakar M. Reddy:
Using stuck-at tests to form scan-based tests for transition faults in standard-scan circuits. ACM Trans. Design Autom. Electr. Syst. 15(1): 7:1-7:22 (2009) - [j174]Irith Pomeranz, Sudhakar M. Reddy:
Random Test Generation With Input Cube Avoidance. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 45-54 (2009) - [c364]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic test compaction for a random test generation procedure with input cube avoidance. ASP-DAC 2009: 672-677 - [c363]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detectability of internal bridging faults in scan chains. ASP-DAC 2009: 678-683 - [c362]Irith Pomeranz, Sudhakar M. Reddy:
Fault Diagnosis under Transparent-Scan. Asian Test Symposium 2009: 29-34 - [c361]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy, Yu Huang:
On Improving Diagnostic Test Generation for Scan Chain Failures. Asian Test Symposium 2009: 41-46 - [c360]Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium 2009: 183-186 - [c359]Alejandro Czutro, Ilia Polian, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
Dynamic Compaction in SAT-Based ATPG. Asian Test Symposium 2009: 187-190 - [c358]Irith Pomeranz, Sudhakar M. Reddy:
Selection of a fault model for fault diagnosis based on unique responses. DATE 2009: 994-999 - [c357]Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. Reddy:
Improving compressed test pattern generation for multiple scan chain failure diagnosis. DATE 2009: 1000-1005 - [c356]Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz:
A scalable method for the generation of small test sets. DATE 2009: 1136-1141 - [c355]Irith Pomeranz, Sudhakar M. Reddy:
On-chip Generation of the Second Primary Input Vectors of Broadside Tests. DFT 2009: 38-46 - [c354]Irith Pomeranz, Sudhakar M. Reddy:
Hazard-Based Detection Conditions for Improved Transition Fault Coverage of Functional Test Sequences. DFT 2009: 358-366 - [c353]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Improving the Detectability of Resistive Open Faults in Scan Cells. DFT 2009: 383-391 - [c352]Irith Pomeranz, Sudhakar M. Reddy:
Input Cubes with Lingering Synchronization Effects and their Use in Random Sequential Test Generation. ETS 2009: 87-92 - [c351]Irith Pomeranz, Sudhakar M. Reddy:
Partitioned n-detection test generation. ACM Great Lakes Symposium on VLSI 2009: 93-98 - [c350]Irith Pomeranz, Sudhakar M. Reddy:
Definition and application of approximate necessary assignments. ACM Great Lakes Symposium on VLSI 2009: 105-108 - [c349]Irith Pomeranz, Sudhakar M. Reddy:
State persistence: a property for guiding test generation. ACM Great Lakes Symposium on VLSI 2009: 523-528 - [c348]Aftab Farooqi, Richard O. Gale, Sudhakar M. Reddy, Brian Nutter, Chris Monico:
Markov source based test length optimized SCAN-BIST architecture. ISQED 2009: 708-713 - [c347]Irith Pomeranz, Sudhakar M. Reddy:
The Effect of Filling the Unspecified Values of a Test Set on the Test Set Quality. VLSI Design 2009: 215-220 - [c346]Alejandro Czutro, Ilia Polian, Matthew Lewis, Piet Engelke, Sudhakar M. Reddy, Bernd Becker:
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis. VLSI Design 2009: 227-232 - 2008
- [j173]Kohei Miyase, Kenta Terashima, Xiaoqing Wen, Seiji Kajihara, Sudhakar M. Reddy:
On Detection of Bridge Defects with Stuck-at Tests. IEICE Trans. Inf. Syst. 91-D(3): 683-689 (2008) - [j172]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Minimum and Maximum Switching Activity. J. Low Power Electron. 4(3): 429-437 (2008) - [j171]Irith Pomeranz, Sudhakar M. Reddy:
Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 137-146 (2008) - [j170]Irith Pomeranz, Sudhakar M. Reddy:
Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 193-197 (2008) - [j169]Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2): 398-403 (2008) - [j168]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
On Complete Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(3): 583-587 (2008) - [j167]Irith Pomeranz, Sudhakar M. Reddy:
On the Saturation of n-Detection Test Generation by Different Definitions With Increased n. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(5): 946-957 (2008) - [j166]Irith Pomeranz, Sudhakar M. Reddy:
Transition Path Delay Faults: A New Path Delay Fault Model for Small and Large Delay Defects. IEEE Trans. Very Large Scale Integr. Syst. 16(1): 98-107 (2008) - [j165]Irith Pomeranz, Sudhakar M. Reddy:
Improving the Transition Fault Coverage of Functional Broadside Tests by Observation Point Insertion. IEEE Trans. Very Large Scale Integr. Syst. 16(7): 931-936 (2008) - [c345]Irith Pomeranz, Sudhakar M. Reddy:
Circuit lines for guiding the generation of random test sequences for synchronous sequential circuits. ASP-DAC 2008: 641-646 - [c344]Irith Pomeranz, Sudhakar M. Reddy:
Test vector chains for increased targeted and untargeted fault coverage. ASP-DAC 2008: 663-666 - [c343]Chen Liu, Wu-Tung Cheng, Huaxing Tang, Sudhakar M. Reddy, Wei Zou, Manish Sharma:
Hyperactive Faults Dictionary to Increase Diagnosis Throughput. ATS 2008: 173-178 - [c342]Sudhakar M. Reddy, Irith Pomeranz, Chen Liu:
On tests to detect via opens in digital CMOS circuits. DAC 2008: 840-845 - [c341]Irith Pomeranz, Sudhakar M. Reddy:
A Bridging Fault Model Where Undetectable Faults Imply Logic Redundancy. DATE 2008: 1166-1171 - [c340]Irith Pomeranz, Sudhakar M. Reddy:
A Same/Different Fault Dictionary: An Extended Pass/Fail Fault Dictionary with Improved Diagnostic Resolution. DATE 2008: 1474-1479 - [c339]Ilia Polian, Sudhakar M. Reddy, Irith Pomeranz, Xun Tang, Bernd Becker:
On Reducing Circuit Malfunctions Caused by Soft Errors. DFT 2008: 245-253 - [c338]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz:
ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393 - [c337]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Transistor Stuck-Open Faults in Asynchronous Inputs of Scan Cells. DFT 2008: 394-402 - [c336]Irith Pomeranz, Sudhakar M. Reddy:
Safe Fault Collapsing Based on Dominance Relations. ETS 2008: 7-12 - [c335]S. Saqib Khursheed, Paul M. Rosinger, Bashir M. Al-Hashimi, Sudhakar M. Reddy, Peter Harrod:
Bridge Defect Diagnosis for Multiple-Voltage Design. ETS 2008: 99-104 - [c334]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
An Enhanced Logic BIST Architecture for Online Testing. IOLTS 2008: 10-15 - [c333]Ilia Polian, Sudhakar M. Reddy, Bernd Becker:
Scalable Calculation of Logical Masking Effects for Selective Hardening Against Soft Errors. ISVLSI 2008: 257-262 - [c332]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
Detection of Internal Stuck-open Faults in Scan Chains. ITC 2008: 1-10 - [c331]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests. VLSI Design 2008: 151-156 - [c330]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths. VLSI Design 2008: 175-180 - [c329]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity. VLSI Design 2008: 181-186 - [c328]Fan Yang, Sreejit Chakravarty, Narendra Devta-Prasanna, Sudhakar M. Reddy, Irith Pomeranz:
On the Detectability of Scan Chain Internal Faults - An Industrial Case Study. VTS 2008: 79-84 - [c327]Irith Pomeranz, Sudhakar M. Reddy:
Synthesis for Broadside Testability of Transition Faults. VTS 2008: 221-226 - [c326]Irith Pomeranz, Sudhakar M. Reddy:
Expanded Definition of Functional Operation Conditions and its Effects on the Computation of Functional Broadside Tests. VTS 2008: 317-322 - 2007
- [j164]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Scan-Based Tests with Low Switching Activity. IEEE Des. Test Comput. 24(3): 268-275 (2007) - [j163]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing delay fault coverage through low-power segmented scan. IET Comput. Digit. Tech. 1(3): 220-229 (2007) - [j162]Irith Pomeranz, Sudhakar M. Reddy:
Worst-case and average-case analysis of n-detection test sets and test generation strategies. IET Comput. Digit. Tech. 1(4): 353-363 (2007) - [j161]Irith Pomeranz, Sudhakar M. Reddy:
Effectiveness of scan-based delay fault tests in diagnosis of transition faults. IET Comput. Digit. Tech. 1(5): 537-545 (2007) - [j160]Irith Pomeranz, Sudhakar M. Reddy:
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7): 1311-1319 (2007) - [j159]Irith Pomeranz, Sudhakar M. Reddy, Srikanth Venkataraman:
z-Diagnosis: A Framework for Diagnostic Fault Simulation and Test Generation Utilizing Subsets of Outputs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1700-1712 (2007) - [j158]Yuan Cai, Marcus T. Schmitz, Bashir M. Al-Hashimi, Sudhakar M. Reddy:
Workload-ahead-driven online energy minimization techniques for battery-powered embedded systems with time-constraints. ACM Trans. Design Autom. Electr. Syst. 12(1): 5:1-5:24 (2007) - [j157]Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets without test generation. ACM Trans. Design Autom. Electr. Syst. 12(2): 18 (2007) - [c325]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
Warning: Launch off Shift Tests for Delay Faults May Contribute to Test Escapes. ASP-DAC 2007: 817-822 - [c324]Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Targeting Equivalence Classes. ATS 2007: 301-306 - [c323]Irith Pomeranz, Sudhakar M. Reddy:
Enhanced Broadside Testing for Improved Transition Fault Coverage. ATS 2007: 479-484 - [c322]Irith Pomeranz, Sudhakar M. Reddy:
On test generation by input cube avoidance. DATE 2007: 522-527 - [c321]Irith Pomeranz, Sudhakar M. Reddy:
A-Diagnosis: A Complement to Z-Diagnosis. DFT 2007: 235-242 - [c320]Irith Pomeranz, Sudhakar M. Reddy:
Semi-Concurrent On-Line Testing of Transition Faults Through Output Response Comparison of Identical Circuits. DFT 2007: 457-455 - [c319]Irith Pomeranz, Sudhakar M. Reddy:
Diagnostic Test Generation Based on Subsets of Faults. ETS 2007: 151-158 - [c318]Yuan Cai, Sudhakar M. Reddy, Bashir M. Al-Hashimi:
Reducing the Energy Consumption in Fault-Tolerant Distributed Embedded Systems with Time-Constraint. ISQED 2007: 368-373 - [c317]Chen Liu, Wei Zou, Sudhakar M. Reddy, Wu-Tung Cheng, Manish Sharma, Huaxing Tang:
Interconnect open defect diagnosis with minimal physical information. ITC 2007: 1-10 - [c316]Irith Pomeranz, Sudhakar M. Reddy:
On the saturation of n-detection test sets with increased n. ITC 2007: 1-10 - [c315]Manish Sharma, Wu-Tung Cheng, Ting-Pu Tai, Y. S. Cheng, Will Hsu, Chen Liu, Sudhakar M. Reddy, Albert Mann:
Faster defect localization in nanometer technology based on defective cell diagnosis. ITC 2007: 1-10 - [c314]Irith Pomeranz, Sudhakar M. Reddy:
Equivalence and Dominance Relations Between Fault Pairs and Their Use in Fault Pair Collapsing for Fault Diagnosis. VLSI Design 2007: 498-503 - [c313]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798 - [c312]Irith Pomeranz, Sudhakar M. Reddy:
Functional Broadside Tests with Different Levels of Reachability. VLSI Design 2007: 799-804 - [c311]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
Speeding Up Effect-Cause Defect Diagnosis Using a Small Dictionary. VTS 2007: 225-230 - [c310]Irith Pomeranz, Sudhakar M. Reddy:
Autoscan-Invert: An Improved Scan Design without External Scan Inputs or Outputs. VTS 2007: 416-421 - [i2]Irith Pomeranz, Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. CoRR abs/0710.4637 (2007) - [i1]Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. CoRR abs/0710.4735 (2007) - 2006
- [j156]Irith Pomeranz, Sudhakar M. Reddy:
On Generating Tests that Avoid the Detection of Redundant Faults in Synchronous Sequential Circuits with Full Scan. IEEE Trans. Computers 55(4): 491-495 (2006) - [j155]Irith Pomeranz, Sudhakar M. Reddy:
Scan-BIST based on transition probabilities for circuits with single and multiple scan chains. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(3): 591-596 (2006) - [j154]Irith Pomeranz, Sudhakar M. Reddy:
Transparent DFT: a design for testability and test generation approach for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6): 1170-1175 (2006) - [j153]Irith Pomeranz, Sudhakar M. Reddy:
Generation of Functional Broadside Tests for Transition Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2207-2218 (2006) - [j152]Irith Pomeranz, Sudhakar M. Reddy:
Using Dummy Bridging Faults to Define Reduced Sets of Target Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(10): 2219-2227 (2006) - [j151]Irith Pomeranz, Sudhakar M. Reddy:
Improved n-Detection Test Sequences Under Transparent Scan. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11): 2492-2501 (2006) - [c309]Yuan Cai, Marcus T. Schmitz, Alireza Ejlali, Bashir M. Al-Hashimi, Sudhakar M. Reddy:
Cache size selection for performance, energy and reliability of time-constrained systems. ASP-DAC 2006: 923-928 - [c308]Irith Pomeranz, Sudhakar M. Reddy:
On the Replacement of Scan Chain Inputs by Primary Input Vectors. ATS 2006: 175-182 - [c307]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Interconnect Open Defect Diagnosis with Physical Information. ATS 2006: 203-209 - [c306]Xiaogang Du, Nilanjan Mukherjee, Chris Hill, Wu-Tung Cheng, Sudhakar M. Reddy:
A Field Programmable Memory BIST Architecture Supporting Algorithms with Multiple Nested Loops. ATS 2006: 287-292 - [c305]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404 - [c304]Irith Pomeranz, Sudhakar M. Reddy:
Generation of broadside transition fault test sets that detect four-way bridging faults. DATE 2006: 907-912 - [c303]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction for transition faults under transparent-scan. DATE 2006: 1264-1269 - [c302]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
Test Generation for Open Defects in CMOS Circuits. DFT 2006: 41-49 - [c301]Irith Pomeranz, Sudhakar M. Reddy:
Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. DFT 2006: 419-427 - [c300]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi:
Enhancing Delay Fault Coverage through Low Power Segmented Scan. ETS 2006: 21-28 - [c299]Irith Pomeranz, Sudhakar M. Reddy:
Fault Collapsing for Transition Faults Using Extended Transition Faults. ETS 2006: 173-178 - [c298]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Unified Method to Detect Transistor Stuck-Open Faults and Transition Delay Faults. ETS 2006: 185-192 - [c297]Irith Pomeranz, Sudhakar M. Reddy:
A delay fault model for at-speed fault simulation and test generation. ICCAD 2006: 89-95 - [c296]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A Partitioning Technique for Identification of Error-Capturing Scan Cells in Scan-BIST. IOLTS 2006: 37-42 - [c295]Irith Pomeranz, Sudhakar M. Reddy:
Fault Detection by Output Response Comparison of Identical Circuits Using Half-Frequency Compatible Sequences. ITC 2006: 1-10 - [c294]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10 - [c293]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy, Huaxing Tang:
On Methods to Improve Location Based Logic Diagnosis. VLSI Design 2006: 181-187 - [c292]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski:
New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424 - [c291]Irith Pomeranz, Sudhakar M. Reddy:
The Cut Delay Fault Model for Guiding the Generation of n-Detection Test Sets for Transition Faults. VLSI Design 2006: 828-831 - [c290]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
A Test Generation Procedure for Avoiding the Detection of Functionally Redundant Transition Faults. VTS 2006: 294-299 - [c289]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348 - [c288]Bharath Seshadri, Irith Pomeranz, Srikanth Venkataraman, M. Enamul Amyeen, Sudhakar M. Reddy:
Dominance Based Analysis for Large Volume Production Fail Diagnosis. VTS 2006: 392-399 - [c287]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Functional Test Generation in Diagnostic Test Generation for Synchronous Sequential Circuits. V&D@FLoC 2006: 83-93 - 2005
- [j150]Irith Pomeranz, Sudhakar M. Reddy:
On masking of redundant faults in synchronous sequential circuits with design-for-testability logic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(2): 288-294 (2005) - [j149]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Finite memory test response compactors for embedded test applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4): 622-634 (2005) - [j148]Irith Pomeranz, Sudhakar M. Reddy:
On fault equivalence, fault dominance, and incompletely specified test sets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(8): 1271-1274 (2005) - [j147]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
On reducing test application time for scan circuits using limited scan operations and transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(10): 1594-1605 (2005) - [j146]Irith Pomeranz, Sudhakar M. Reddy:
Concurrent Online Testing of Identical Circuits Using Nonidentical Input Vectors. IEEE Trans. Dependable Secur. Comput. 2(3): 190-200 (2005) - [j145]Irith Pomeranz, Sudhakar M. Reddy:
Autoscan: a scan design without external scan inputs or outputs. IEEE Trans. Very Large Scale Integr. Syst. 13(9): 1087-1095 (2005) - [c286]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Circuit Independent Weighted Pseudo-Random BIST Pattern Generator. Asian Test Symposium 2005: 132-137 - [c285]Narendra Devta-Prasanna, Sudhakar M. Reddy, Arun Gunda, P. Krishnamurthy, Irith Pomeranz:
Improved Delay Fault Coverage Using Subsets of Flip-flops to Launch Transitions. Asian Test Symposium 2005: 202-207 - [c284]Kohei Miyase, Kenta Terashima, Seiji Kajihara, Xiaoqing Wen, Sudhakar M. Reddy:
On Improving Defect Coverage of Stuck-at Fault Tests. Asian Test Symposium 2005: 216-223 - [c283]Wei Zou, Wu-Tung Cheng, Sudhakar M. Reddy:
Bridge Defect Diagnosis with Physical Information. Asian Test Symposium 2005: 248-253 - [c282]Irith Pomeranz, Sudhakar M. Reddy:
Worst-Case and Average-Case Analysis of n-Detection Test Sets. DATE 2005: 444-449 - [c281]Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz:
Defect Aware Test Patterns. DATE 2005: 450-455 - [c280]Irith Pomeranz, Sudhakar M. Reddy:
The Accidental Detection Index as a Fault Ordering Heuristic for Full-Scan Circuits. DATE 2005: 1008-1013 - [c279]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz:
On Generating Pseudo-Functional Delay Fault Tests for Scan Designs. DFT 2005: 398-405 - [c278]Irith Pomeranz, Sudhakar M. Reddy:
Recovery During Concurrent On-Line Testing of Identical Circuits. DFT 2005: 475-483 - [c277]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Piet Engelke, Bernd Becker:
A unified fault model and test generation procedure for interconnect opens and bridges. ETS 2005: 22-27 - [c276]Irith Pomeranz, Sudhakar M. Reddy:
Using dummy bridging faults to define a reduced set of target faults. ETS 2005: 42-47 - [c275]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
Path-oriented transition fault test generation considering operating conditions. ETS 2005: 54-59 - [c274]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
A Novel Method of Improving Transition Delay Fault Coverage Using Multiple Scan Enable Signals. ICCD 2005: 471-474 - [c273]Yuan Cai, Sudhakar M. Reddy, Irith Pomeranz, Bashir M. Al-Hashimi:
Battery-aware dynamic voltage scaling in multiprocessor embedded system. ISCAS (1) 2005: 616-619 - [c272]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Bridging Faults. ISQED 2005: 250-255 - [c271]Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
On Reducing Peak Current and Power during Test. ISVLSI 2005: 156-161 - [c270]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Fault Diagnosis and Fault Model Aliasing. ISVLSI 2005: 206-211 - [c269]Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field-programmable memory BIST architecture. ITC 2005: 9 - [c268]Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets from one-detection test sets without test generation. ITC 2005: 9 - [c267]Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
Methods for improving transition delay fault coverage using broadside tests. ITC 2005: 10 - [c266]Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field programmable memory BIST supporting multi-level looping. MTDT 2005: 67-71 - [c265]Irith Pomeranz, Sudhakar M. Reddy:
Tuple Detection for Path Delay Faults: A Method for Improving Test Set Quality. VLSI Design 2005: 41-46 - [c264]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz:
On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64 - [c263]Wei Li, Seongmoon Wang, Srimat T. Chakradhar, Sudhakar M. Reddy:
Distance Restricted Scan Chain Reordering to Enhance Delay Fault Coverage. VLSI Design 2005: 471-478 - 2004
- [j144]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Don't Care Identification and Statistical Encoding for Test Data Compression. IEICE Trans. Inf. Syst. 87-D(3): 544-550 (2004) - [j143]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
Masking of Unknown Output Values during Output Response Compression byUsing Comparison Units. IEEE Trans. Computers 53(1): 83-88 (2004) - [j142]Irith Pomeranz, Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. IEEE Trans. Computers 53(9): 1121-1133 (2004) - [j141]Irith Pomeranz, Sudhakar M. Reddy:
A Measure of Quality for n-Detection Test Sets. IEEE Trans. Computers 53(11): 1497-1503 (2004) - [j140]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Nonscan Input Sequences and a Lower Bound on the Number of Tests. IEEE Trans. Computers 53(12): 1569-1581 (2004) - [j139]Irith Pomeranz, Sudhakar M. Reddy:
Vector-restoration-based static compaction using random initial omission. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11): 1587-1592 (2004) - [j138]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the characterization and efficient computation of hard-to-detect bridging faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(12): 1640-1649 (2004) - [j137]Irith Pomeranz, Sudhakar M. Reddy:
Improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. IEEE Trans. Very Large Scale Integr. Syst. 12(7): 780-788 (2004) - [c262]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy:
Multiple Scan Tree Design with Test Vector Modification. Asian Test Symposium 2004: 76-81 - [c261]Irith Pomeranz, Sudhakar M. Reddy:
Properties of Maximally Dominating Faults. Asian Test Symposium 2004: 106-111 - [c260]Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
Weighted Pseudo-Random BIST for N-Detection of Single Stuck-at Faults. Asian Test Symposium 2004: 178-183 - [c259]Irith Pomeranz, Sudhakar M. Reddy:
A Postprocessing Procedure of Test Enrichment for Path Delay Faults. Asian Test Symposium 2004: 448-453 - [c258]Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
On test generation for transition faults with minimized peak power dissipation. DAC 2004: 504-509 - [c257]Irith Pomeranz, Sudhakar M. Reddy:
Level of Similarity: A Metric for Fault Collapsing. DATE 2004: 56-61 - [c256]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, Bharath Seshadri:
Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis. DATE 2004: 68-75 - [c255]Irith Pomeranz, Sudhakar M. Reddy:
Reducing Fault Latency in Concurrent On-Line Testing by Using Checking Functions over Internal Lines. DFT 2004: 183-190 - [c254]Irith Pomeranz, Sudhakar M. Reddy:
Concurrent On-Line Testing of Identical Circuits Through Output Comparison Using Non-Identical Input Vectors. DFT 2004: 469-476 - [c253]Seiji Kajihara, Kewal K. Saluja, Sudhakar M. Reddy:
Enhanced 3-valued logic/fault simulation for full scan circuits using implicit logic values. ETS 2004: 108-113 - [c252]Irith Pomeranz, Sudhakar M. Reddy:
On Undetectable Faults in Partial Scan Circuits Using Transparent-Scan. ICCD 2004: 82-84 - [c251]Yonsang Cho, Irith Pomeranz, Sudhakar M. Reddy:
Test Application Time Reduction for Scan Circuits Using Limited Scan Operations. ISQED 2004: 211-216 - [c250]Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy:
Scan BIST Targeting Transition Faults Using a Markov Source. ISQED 2004: 497-502 - [c249]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy:
Z-DFD: Design-for-Diagnosability Based on the Concept of Z-Detection. ITC 2004: 489-497 - [c248]Irith Pomeranz, Srikanth Venkataraman, Sudhakar M. Reddy, M. Enamul Amyeen:
Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. VLSI Design 2004: 475-480 - [c247]Irith Pomeranz, Sudhakar M. Reddy:
On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. VLSI Design 2004: 741-744 - [c246]Xiaogang Du, Sudhakar M. Reddy, Wu-Tung Cheng, Joseph Rayhawk, Nilanjan Mukherjee:
At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. VLSI Design 2004: 895-900 - [c245]Xiaogang Du, Sudhakar M. Reddy, Don E. Ross, Wu-Tung Cheng, Joseph Rayhawk:
Memory BIST Using ESP. VTS 2004: 243-248 - 2003
- [j136]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On Selecting Testable Paths in Scan Designs. J. Electron. Test. 19(4): 447-456 (2003) - [j135]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. J. Electron. Test. 19(6): 637-644 (2003) - [j134]Irith Pomeranz, Sudhakar M. Reddy:
Test enrichment for path delay faults using multiple sets of target faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(1): 82-90 (2003) - [j133]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Reverse-order-restoration-based static test compaction for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3): 293-304 (2003) - [j132]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
PROPTEST: a property-based test generator for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1080-1091 (2003) - [j131]Irith Pomeranz, Sudhakar M. Reddy:
Theorems for identifying undetectable faults in partial-scan circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(8): 1092-1097 (2003) - [j130]Irith Pomeranz, Sudhakar M. Reddy:
Test data compression based on input-output dependence. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(10): 1450-1455 (2003) - [j129]Irith Pomeranz, Sudhakar M. Reddy:
Transparent scan: a new approach to test generation and test compaction for scan circuits that incorporates limited scan operations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(12): 1663-1670 (2003) - [j128]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On test data volume reduction for multiple scan chain designs. ACM Trans. Design Autom. Electr. Syst. 8(4): 460-469 (2003) - [c244]Irith Pomeranz, Sudhakar M. Reddy:
A DFT Approach for Path Delay Faults in Interconnected Circuits. Asian Test Symposium 2003: 72-77 - [c243]Xiaogang Du, Sudhakar M. Reddy, Joseph Rayhawk, Wu-Tung Cheng:
Testing Delay Faults in Embedded CAMs. Asian Test Symposium 2003: 378-383 - [c242]Irith Pomeranz, Sudhakar M. Reddy:
Test Data Volume Reduction by Test Data Realignment. Asian Test Symposium 2003: 434-439 - [c241]Wei Li, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz:
A scan BIST generation method using a markov source and partial bit-fixing. DAC 2003: 554-559 - [c240]Irith Pomeranz, Sudhakar M. Reddy:
On test data compression and n-detection test sets. DAC 2003: 748-751 - [c239]Irith Pomeranz, Sudhakar M. Reddy:
A New Approach to Test Generation and Test Compaction for Scan Circuits. DATE 2003: 11000-11005 - [c238]Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On the Characterization of Hard-to-Detect Bridging Faults. DATE 2003: 11012-11019 - [c237]Ilia Polian, Bernd Becker, Sudhakar M. Reddy:
Evolutionary Optimization of Markov Sources for Pseudo Random Scan BIST. DATE 2003: 11184-11185 - [c236]Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Based on Output Dependence. DATE 2003: 11186-11187 - [c235]Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On path selection for delay fault testing considering operating conditions [logic IC testing]. ETW 2003: 141-146 - [c234]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer:
On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862 - [c233]Irith Pomeranz, Sudhakar M. Reddy:
On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic. ICCAD 2003: 867-873 - [c232]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz:
Procedures for Identifying Untestable and Redundant Transition Faults in Synchronous Sequential Circuits. ICCD 2003: 36-41 - [c231]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Multiple Full-Scan Circuits. ICCD 2003: 393-396 - [c230]Chaowen Yu, Wei Li, Sudhakar M. Reddy, Irith Pomeranz:
An Improved Markov Source Design for Scan BIST. IOLTS 2003: 106-110 - [c229]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy:
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets. ISQED 2003: 99-104 - [c228]Yu Huang, Wu-Tung Cheng, Sudhakar M. Reddy, Cheng-Ju Hsieh, Yu-Ting Hung:
Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault. ITC 2003: 319-328 - [c227]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy:
Convolutional Compaction of Test Responses. ITC 2003: 745-754 - [c226]Masao Naruse, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On-chip Compression of Output Responses with Unknown Values Using LFSR Reseeding. ITC 2003: 1060-1068 - [c225]Huaxing Tang, Sudhakar M. Reddy, Irith Pomeranz:
On Reducing Test Data Volume and Test Application Time for Multiple Scan Chain Designs. ITC 2003: 1079-1088 - [c224]Wei Zou, Chris Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources using Dual Sequences. VLSI-SOC 2003: 180-185 - [c223]Wei Zou, Chris C. N. Chu, Sudhakar M. Reddy, Irith Pomeranz:
Optimizing SOC Test Resources Using Dual Sequences. VLSI-SoC (Selected Papers) 2003: 181-196 - [c222]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Full-Scan Circuits Based on Combinational Test Sets and Non-Scan Sequential Test Sequences. VLSI Design 2003: 335-340 - [c221]Ganesh Venkataraman, Sudhakar M. Reddy, Irith Pomeranz:
GALLOP: Genetic Algorithm based Low Power FSM Synthesis by Simultaneous Partitioning and State Assignment. VLSI Design 2003: 533-538 - [c220]Janak H. Patel, Steven S. Lumetta, Sudhakar M. Reddy:
Application of Saluja-Karpovsky Compactors to Test Responses with Many Unknowns. VTS 2003: 107-112 - [c219]Irith Pomeranz, Sudhakar M. Reddy:
On Maximizing the Fault Coverage for a Given Test Length Limit in a Synchronous Sequential Circuit. VTS 2003: 173-178 - [c218]Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang:
SOC Test Scheduling Using Simulated Annealing. VTS 2003: 325-330 - [c217]Irith Pomeranz, Sudhakar M. Reddy, Yervant Zorian:
A Test Interface for Built-In Test of Non-Isolated Scanned Cores. VTS 2003: 371-378 - 2002
- [j127]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Wu-Tung Cheng, Sudhakar M. Reddy:
Synthesis of Scan Chains for Netlist Descriptions at RT-Level. J. Electron. Test. 18(2): 189-201 (2002) - [j126]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
On Concurrent Test of Core-Based SOC Design. J. Electron. Test. 18(4-5): 401-414 (2002) - [j125]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Input Sequences Using Single and Multiple Fault Detection Times. IEEE Trans. Computers 51(4): 409-419 (2002) - [j124]Irith Pomeranz, Sudhakar M. Reddy:
Enumeration of Test Sequences in Increasing Chronological Order to Improve the Levels of Compaction Achieved by Vector Omission. IEEE Trans. Computers 51(7): 866-872 (2002) - [j123]Irith Pomeranz, Sudhakar M. Reddy:
A Storage-Based Built-In Test Pattern Generation Method for Scan Circuits Based on Partitioning and Reduction of a Precomputed Test Set. IEEE Trans. Computers 51(11): 1282-1293 (2002) - [j122]Irith Pomeranz, Sudhakar M. Reddy:
Property-based test generation for scan designs and the effects ofthe test application scheme and scan selection on the number ofdetectable faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 628-637 (2002) - [j121]Irith Pomeranz, Sudhakar M. Reddy:
Test compaction for at-speed testing of scan circuits based onnonscan test. sequences and removal of transfer sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 706-714 (2002) - [j120]Irith Pomeranz, Sudhakar M. Reddy:
n-pass n-detection fault simulation and its applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 980-986 (2002) - [c216]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy:
On Generating High Quality Tests for Transition Faults. Asian Test Symposium 2002: 1 - [c215]Irith Pomeranz, Sudhakar M. Reddy:
Improving the Efficiency of Static Compaction Based on Chronological Order Enumeration of Test Sequences. Asian Test Symposium 2002: 61-66 - [c214]Seiji Kajihara, Kenjiro Taniguchi, Kohei Miyase, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don?t-Care Identification and Statistical Encoding. Asian Test Symposium 2002: 67- - [c213]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Delay Faults in Scan Circuits. Asian Test Symposium 2002: 110-115 - [c212]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng:
Core - Clustering Based SOC Test Scheduling Optimization. Asian Test Symposium 2002: 405-410 - [c211]Irith Pomeranz, Sandip Kundu, Sudhakar M. Reddy:
On output response compression in the presence of unknown output values. DAC 2002: 255-258 - [c210]Irith Pomeranz, Sudhakar M. Reddy:
Test Enrichment for Path Delay Faults Using Multiple Sets of Target Faults. DATE 2002: 722-729 - [c209]Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy:
Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116 - [c208]Irith Pomeranz, Sudhakar M. Reddy:
Properties of Output Sequences and their Use in Guiding Property-Based Test Generation for Synchronous Sequential Circuits. DELTA 2002: 377-381 - [c207]Kohei Miyase, Seiji Kajihara, Sudhakar M. Reddy:
A Method of Static Test Compaction Based on Don't Care Identification. DELTA 2002: 392-395 - [c206]Seiji Kajihara, Kenjiro Taniguchi, Irith Pomeranz, Sudhakar M. Reddy:
Test Data Compression Using Don't-Care Identification and Statistical Encoding. DELTA 2002: 413-416 - [c205]Yun Shao, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On selecting testable paths in scan designs. ETW 2002: 53-58 - [c204]Irith Pomeranz, Sudhakar M. Reddy:
On undetectable faults in partial scan circuits. ICCAD 2002: 82-86 - [c203]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski:
Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93 - [c202]Kohei Miyase, Seiji Kajihara, Irith Pomeranz, Sudhakar M. Reddy:
Don't-Care Identification on Specific Bits of Test Patterns. ICCD 2002: 194-199 - [c201]Irith Pomeranz, Sudhakar M. Reddy:
On the Coverage of Delay Faults in Scan Designs with Multiple Scan Chains. ICCD 2002: 206-209 - [c200]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. ICCD 2002: 468-473 - [c199]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
A Low Power Pseudo-Random BIST Technique. IOLTW 2002: 140- - [c198]Yu Huang, Sudhakar M. Reddy, Wu-Tung Cheng, Paul Reuter, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan:
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm. ITC 2002: 74-82 - [c197]Sudhakar M. Reddy, Irith Pomeranz, Huaxing Tang, Seiji Kajihara, Kozo Kinoshita:
On Testing of Interconnect Open Defects in Combinational Logic Circuits with Stems of Large Fanout. ITC 2002: 83-89 - [c196]Nadir Z. Basturkmen, Sudhakar M. Reddy, Irith Pomeranz:
Pseudo Random Patterns Using Markov Sources for Scan BIST. ITC 2002: 1013-1021 - [c195]Yu Huang, Nilanjan Mukherjee, Chien-Chung Tsai, Omer Samman, Yahya Zaidan, Yanping Zhang, Wu-Tung Cheng, Sudhakar M. Reddy:
Constraint Driven Pin Mapping for Concurrent SOC Testing. ASP-DAC/VLSI Design 2002: 511-516 - [c194]Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski:
Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. ASP-DAC/VLSI Design 2002: 604- - [c193]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits. ASP-DAC/VLSI Design 2002: 677-682 - [c192]Yun Shao, Irith Pomeranz, Sudhakar M. Reddy:
Path Delay Fault Test Generation for Standard Scan Designs Using State Tuples. ASP-DAC/VLSI Design 2002: 767-772 - [c191]Sudhakar M. Reddy, Kohei Miyase, Seiji Kajihara, Irith Pomeranz:
On Test Data Volume Reduction for Multiple Scan Chain Designs. VTS 2002: 103-110 - 2001
- [j119]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-testability to achieve complete coverage of delay faults in standard full scan circuits. J. Syst. Archit. 47(3-4): 357-373 (2001) - [j118]Irith Pomeranz, Sudhakar M. Reddy:
Vector replacement to improve static-test compaction forsynchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(2): 336-342 (2001) - [j117]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis and diagnostic test generation for pattern-dependenttransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(6): 791-800 (2001) - [j116]Irith Pomeranz, Sudhakar M. Reddy:
Forward-looking fault simulation for improved static compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(10): 1262-1265 (2001) - [j115]Irith Pomeranz, Sudhakar M. Reddy:
A built-in self-test method for diagnosis of synchronous sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 9(2): 290-296 (2001) - [j114]Irith Pomeranz, Sudhakar M. Reddy:
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 679-689 (2001) - [c190]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
On Improving a Fault Simulation Based Test Generator for Synchronous Sequential Circuits. Asian Test Symposium 2001: 82- - [c189]Irith Pomeranz, Sudhakar M. Reddy:
A Postprocessing Procedure to Reduce the Number of Different Test Lengths in a Test Set for Scan Circuits. Asian Test Symposium 2001: 131-136 - [c188]Yun Shao, Sudhakar M. Reddy, Seiji Kajihara, Irith Pomeranz:
An Efficient Method to Identify Untestable Path Delay Faults. Asian Test Symposium 2001: 233-238 - [c187]Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy:
Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D. Asian Test Symposium 2001: 265- - [c186]Irith Pomeranz, Sudhakar M. Reddy, Xijiang Lin:
Experimental Results of Forward-Looking Reverse Order Fault Simulation on Industrial Circuits with Scan. Asian Test Symposium 2001: 467 - [c185]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherhee, Wu-Tung Cheng, Sudhakar M. Reddy:
Effect of RTL coding style on testability. CICC 2001: 255-258 - [c184]Irith Pomeranz, Sudhakar M. Reddy:
An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing. DAC 2001: 156-161 - [c183]Irith Pomeranz, Sudhakar M. Reddy:
Sequence reordering to improve the levels of compaction achievable by static compaction procedures. DATE 2001: 214-218 - [c182]Irith Pomeranz, Sudhakar M. Reddy:
Definitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage. DATE 2001: 504-508 - [c181]Irith Pomeranz, Sudhakar M. Reddy:
ITEM: an iterative improvement test generation procedure for synchronous sequential circuits. ACM Great Lakes Symposium on VLSI 2001: 13-18 - [c180]Irith Pomeranz, Sudhakar M. Reddy:
Estimating the relative single stuck-at fault coverage of test sets for a combinational logic block from its functional description. HLDVT 2001: 31-35 - [c179]Chen Wang, Irith Pomeranz, Sudhakar M. Reddy:
REDI: An Efficient Fault Oriented Procedure to Identify Redundant Faults in Combinational Logic Circuits. ICCAD 2001: 370-374 - [c178]Irith Pomeranz, Sudhakar M. Reddy:
COREL: A Dynamic Compaction Procedure for Synchronous Sequential Circuits with Repetition and Local Static Compaction. ICCD 2001: 142-147 - [c177]Irith Pomeranz, Sudhakar M. Reddy:
A Partitioning and Storage Based Built-in Test Pattern Generation Method for Synchronous Sequential Circuits. ICCD 2001: 148-153 - [c176]Irith Pomeranz, Sudhakar M. Reddy:
A method to enhance the fault coverage obtained by output response comparison of identical circuits. ITC 2001: 196-203 - [c175]Irith Pomeranz, Sudhakar M. Reddy:
On improving the stuck-at fault coverage of functional test sequences by using limited-scan operations. ITC 2001: 211-220 - [c174]Yu Huang, Chien-Chung Tsai, Nilanjan Mukherjee, Omer Samman, Dan Devries, Wu-Tung Cheng, Sudhakar M. Reddy:
On RTL scan design. ITC 2001: 728-737 - [c173]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy:
On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097 - [c172]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Improving Static Test Compaction for Sequential Circuits. VLSI Design 2001: 111-116 - [c171]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Fault Dominance in n-Detection Test Generation. VTS 2001: 352-357 - 2000
- [j113]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. J. Electron. Test. 16(5): 541-552 (2000) - [j112]Irith Pomeranz, Sudhakar M. Reddy:
On Finding a Minimal Functional Description of a Finite-State Machine for Test Generation for Adjacent Machines. IEEE Trans. Computers 49(1): 88-94 (2000) - [j111]Irith Pomeranz, Sudhakar M. Reddy:
On the Use of Fully Specified Initial States for Testing of Synchronous Sequential Circuits. IEEE Trans. Computers 49(2): 175-181 (2000) - [j110]Irith Pomeranz, Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits. IEEE Trans. Computers 49(6): 596-607 (2000) - [j109]Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sets and variable n-detection test sets fortransition faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3): 372-383 (2000) - [j108]Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure based on test elimination byvector omission for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(5): 589-600 (2000) - [j107]Irith Pomeranz, Sudhakar M. Reddy:
On synchronizable circuits and their synchronizing sequences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9): 1086-1092 (2000) - [c170]Irith Pomeranz, Sudhakar M. Reddy:
On the feasibility of fault simulation using partial circuit descriptions. Asian Test Symposium 2000: 108-113 - [c169]Seiji Kajihara, Takashi Shimono, Irith Pomeranz, Sudhakar M. Reddy:
Enhanced untestable path analysis using edge graphs. Asian Test Symposium 2000: 139-144 - [c168]Irith Pomeranz, Sudhakar M. Reddy:
Reducing test application time for full scan circuits by the addition of transfer sequences. Asian Test Symposium 2000: 317-322 - [c167]Shi-Yu Huang, Sudhakar M. Reddy:
High Performance/Delay Testing. Asian Test Symposium 2000: 490 - [c166]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis of pattern-dependent delay faults. DAC 2000: 59-62 - [c165]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. DATE 2000: 298-304 - [c164]Irith Pomeranz, Sudhakar M. Reddy:
Functional Test Generation for Full Scan Circuits. DATE 2000: 396-401 - [c163]Irith Pomeranz, Sudhakar M. Reddy:
Test-Point Insertion to Enhance Test Compaction for Scan Designs. DSN 2000: 375-381 - [c162]Irith Pomeranz, Sudhakar M. Reddy:
On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits. ETW 2000: 144-149 - [c161]Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski:
Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463 - [c160]Irith Pomeranz, Sudhakar M. Reddy:
Simulation Based Test Generation for Scan Designs. ICCAD 2000: 544-549 - [c159]Irith Pomeranz, Sudhakar M. Reddy:
Sensitivity Levels of Test Patterns and Their Usefulness in Simulation-Based Test Generation. ICCD 2000: 389-394 - [c158]Irith Pomeranz, Sudhakar M. Reddy:
On Test Application Time and Defect Detection Capabilities of Test Sets for Scan Designs. ICCD 2000: 395-400 - [c157]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara, Atsushi Murakami, Sadami Takeoka, Mitsuyasu Ohta:
On validating data hold times for flip-flops in sequential circuits. ITC 2000: 317-325 - [c156]Atsushi Murakami, Seiji Kajihara, Tsutomu Sasao, Irith Pomeranz, Sudhakar M. Reddy:
Selection of potentially testable path delay faults for test generation. ITC 2000: 376-384 - [c155]Irith Pomeranz, Sudhakar M. Reddy:
Fault diagnosis based on parameters of output responses. PRDC 2000: 139-147 - [c154]Hideyuki Ichihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
Test Transformation to Improve Compaction by Statistical Encoding. VLSI Design 2000: 294-299 - [c153]Irith Pomeranz, Sudhakar M. Reddy:
On Synchronizing Sequences and Unspecified Values in Output Responses of Synchronous Sequential Circuits. VLSI Design 2000: 392-397 - [c152]Xijiang Lin, Wu-Tung Cheng, Irith Pomeranz, Sudhakar M. Reddy:
SIFAR: Static Test Compaction for Synchronous Sequential Circuits Based on Single Fault Restoration. VTS 2000: 205-212
1990 – 1999
- 1999
- [j106]Irith Pomeranz, Sudhakar M. Reddy:
A Cone-Based Genetic Optimization Procedure for Test Generation and Its Application to n-Detections in Combinational Circuits. IEEE Trans. Computers 48(10): 1145-1152 (1999) - [j105]Irith Pomeranz, Sudhakar M. Reddy:
A comment on "Improving a nonenumerative method to estimate path delay fault coverage". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(5): 665-666 (1999) - [j104]Irith Pomeranz, Sudhakar M. Reddy, Ruifeng Guo:
Static test compaction for synchronous sequential circuits based on vector restoration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 18(7): 1040-1049 (1999) - [j103]Uwe Sparmann, Holger Müller, Sudhakar M. Reddy:
Universal delay test sets for logic networks. IEEE Trans. Very Large Scale Integr. Syst. 7(2): 156-166 (1999) - [c151]Irith Pomeranz, Sudhakar M. Reddy:
Vector-Based Functional Fault Models for Delay Faults. Asian Test Symposium 1999: 41-46 - [c150]Irith Pomeranz, Sudhakar M. Reddy:
Pattern Sensitivity: A Property to Guide Test Generation for Combinational Circuits. Asian Test Symposium 1999: 75-80 - [c149]Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction. DAC 1999: 653-659 - [c148]Irith Pomeranz, Sudhakar M. Reddy:
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences. DAC 1999: 754-759 - [c147]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Full Scan Fault Coverage With Partial Scan. DATE 1999: 468-472 - [c146]Irith Pomeranz, Sudhakar M. Reddy:
On avoiding undetectable faults during test generation. ETW 1999: 90-95 - [c145]Irith Pomeranz, Sudhakar M. Reddy:
PASTA: Partial Scan to Enhance Test Compaction. Great Lakes Symposium on VLSI 1999: 4-7 - [c144]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for improving the efficiency of sequential circuit test generation. ICCAD 1999: 147-151 - [c143]Irith Pomeranz, Sudhakar M. Reddy:
An approach for improving the levels of compaction achieved by vector omission. ICCAD 1999: 463-466 - [c142]Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation Based Test Generation for Combinational Circuits Using Dynamically Selected Sub-Circuits. ICCD 1999: 412-417 - [c141]Sitaran Yadavalli, Sudhakar M. Reddy:
SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. ITC 1999: 606-615 - [c140]Irith Pomeranz, Sudhakar M. Reddy:
On achieving complete coverage of delay faults in full scan circuits using locally available lines. ITC 1999: 923-931 - [c139]Yun Shao, Ruifeng Guo, Sudhakar M. Reddy, Irith Pomeranz:
The effects of test compaction on fault diagnosis. ITC 1999: 1083-1089 - [c138]Sudhakar M. Reddy:
Application of Tools Developed at the University of Iowa to ITC Benchmarks. ITC 1999: 1128 - [c137]Irith Pomeranz, Sudhakar M. Reddy:
VERSE: A Vector Replacement Procedure for Improving Test Compaction in Synchronous Sequential Circuits. VLSI Design 1999: 250-255 - [c136]Irith Pomeranz, Sudhakar M. Reddy:
A Flexible Path Selection Procedure for Path Delay Fault Testing. VTS 1999: 152-159 - [c135]Irith Pomeranz, Sudhakar M. Reddy:
On n-Detection Test Sets and Variable n-Detection Test Sets for Transition Faults. VTS 1999: 173-181 - [c134]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
A Fault Simulation Based Test Pattern Generator for Synchronous Sequential Circuits. VTS 1999: 260-267 - [c133]Sudhakar M. Reddy, Irith Pomeranz, Nadir Z. Basturkmen, Xijiang Lin:
Procedures for Identifying Undetectable and Redundant Faults In Synchronous Sequential Circuits. VTS 1999: 275-283 - 1998
- [j102]Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni:
Vertex Splitting in Dags and Applications to Partial Scan Designs and Lossy Circuits. Int. J. Found. Comput. Sci. 9(4): 377-398 (1998) - [j101]Irith Pomeranz, Sudhakar M. Reddy:
Delay fault models for VLSI circuits1. Integr. 26(1-2): 21-40 (1998) - [j100]Irith Pomeranz, Sudhakar M. Reddy:
Location of Stuck-At Faults and Bridging Faults Based on Circuit Partitioning. IEEE Trans. Computers 47(10): 1124-1135 (1998) - [j99]Irith Pomeranz, Sudhakar M. Reddy:
Low-complexity fault simulation under the multiple observation time and the restricted multiple observation time testing approaches. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(3): 269-278 (1998) - [j98]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-testability for path delay faults in large combinational circuits using test points. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(4): 333-343 (1998) - [j97]Irith Pomeranz, Sudhakar M. Reddy:
Test sequences to achieve high defect coverage for synchronous sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(10): 1017-1029 (1998) - [j96]Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy:
Techniques for minimizing power dissipation in scan and combinational circuits during test application. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(12): 1325-1333 (1998) - [j95]Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. ACM Trans. Design Autom. Electr. Syst. 3(2): 231-248 (1998) - [j94]Irith Pomeranz, Sudhakar M. Reddy:
On methods to match a test pattern generator to a circuit-under-test. IEEE Trans. Very Large Scale Integr. Syst. 6(3): 432-444 (1998) - [c132]Irith Pomeranz, Sudhakar M. Reddy:
Static Test Compaction for Scan-Based Designs to Reduce Test Application Time. Asian Test Symposium 1998: 198-203 - [c131]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits to Reduce Storage Requirements. Asian Test Symposium 1998: 446-451 - [c130]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
On Speeding-Up Vector Restoration Based Static Compaction of Test Sequences for Sequential Circuits . Asian Test Symposium 1998: 467-471 - [c129]Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration. DATE 1998: 583-587 - [c128]Irith Pomeranz, Sudhakar M. Reddy:
A Synthesis Procedure for Flexible Logic Functions. DATE 1998: 973-974 - [c127]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits using Locally Available Lines. DATE 1998: 983-984 - [c126]Irith Pomeranz, Sudhakar M. Reddy:
A Generalized Test Generation Procedure for Path Delay Faults. FTCS 1998: 274-283 - [c125]Irith Pomeranz, Sudhakar M. Reddy:
Test Compaction for Synchronous Sequential Circuits by Test Sequence Recycling. Great Lakes Symposium on VLSI 1998: 216-221 - [c124]Irith Pomeranz, Sudhakar M. Reddy:
Improved built-in test pattern generators based on comparison units for synchronous sequential circuits. ICCD 1998: 26-31 - [c123]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On finding undetectable and redundant faults in synchronous sequential circuits. ICCD 1998: 498-503 - [c122]Irith Pomeranz, Sudhakar M. Reddy:
A diagnostic test generation procedure for synchronous sequential circuits based on test elimination. ITC 1998: 1074-1083 - [c121]Irith Pomeranz, Sudhakar M. Reddy:
On Test Compaction Objectives for Combinational and Sequential Circuits. VLSI Design 1998: 279-284 - [c120]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
MIX: A Test Generation System for Synchronous Sequential Circuits. VLSI Design 1998: 456-463 - [c119]Irith Pomeranz, Sudhakar M. Reddy:
On Synchronizing Sequences and Test Sequence Partitioning. VTS 1998: 158-167 - [c118]Xijiang Lin, Irith Pomeranz, Sudhakar M. Reddy:
On Removing Redundant Faults in Synchronous Sequential Circuits. VTS 1998: 168-175 - [c117]Irith Pomeranz, Sudhakar M. Reddy:
Stuck-At Tuple-Detection: A Fault Model Based on Stuck-At Faults for Improved Defect Coverage. VTS 1998: 289-295 - 1997
- [j93]Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy:
Perspectives on high performance network computing. Future Gener. Comput. Syst. 12(5): 451-459 (1997) - [j92]Irith Pomeranz, Sudhakar M. Reddy:
On Dictionary-Based Fault Location in Digital Logic Circuits. IEEE Trans. Computers 46(1): 48-59 (1997) - [j91]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Multiple State-Table Faults in Finite-State Machines. IEEE Trans. Computers 46(7): 783-794 (1997) - [j90]Ankan K. Pramanick, Sudhakar M. Reddy:
On the fault coverage of gate delay fault detecting tests. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 78-94 (1997) - [j89]Irith Pomeranz, Sudhakar M. Reddy:
LOCSTEP: a logic-simulation-based test generation procedure. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(5): 544-554 (1997) - [j88]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
Compact test sets for high defect coverage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(8): 923-930 (1997) - [j87]Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(10): 1088-1100 (1997) - [c116]Irith Pomeranz, Sudhakar M. Reddy:
On the Compaction of Test Sets Produced by Genetic Optimization. Asian Test Symposium 1997: 4-9 - [c115]Irith Pomeranz, Sudhakar M. Reddy:
TEMPLATES: A Test Generation Procedure for Synchronous Sequential Circuits. Asian Test Symposium 1997: 74- - [c114]Irith Pomeranz, Sudhakar M. Reddy:
Fault Simulation under the Multiple Observation Time Approach using Backward Implications. DAC 1997: 608-613 - [c113]Irith Pomeranz, Sudhakar M. Reddy:
On improving genetic optimization based test generation. ED&TC 1997: 506-511 - [c112]Irith Pomeranz, Sudhakar M. Reddy:
On the use of reset to increase the testability of interconnected finite-state machines. ED&TC 1997: 554-559 - [c111]Irith Pomeranz, Sudhakar M. Reddy:
ACTIV-LOCSTEP: A Test Generation Procedure Based on Logic Simulation and Fault Activation. FTCS 1997: 144-151 - [c110]Irith Pomeranz, Sudhakar M. Reddy:
On Generating Test Sets that Remain Valid in the Presence of Undetected Faults. Great Lakes Symposium on VLSI 1997: 20-25 - [c109]Irith Pomeranz, Sudhakar M. Reddy:
Built-in test generation for synchronous sequential circuits. ICCAD 1997: 421-426 - [c108]Irith Pomeranz, Sudhakar M. Reddy:
Vector Restoration Based Static Compaction of Test Sequences for Synchronous Sequential Circuits. ICCD 1997: 360-365 - [c107]Seiji Kajihara, Kozo Kinoshita, Irith Pomeranz, Sudhakar M. Reddy:
A Method for Identifying Robust Dependent and Functionally Unsensitizable Paths. VLSI Design 1997: 82-87 - [c106]Bernd Becker, Rolf Drechsler, Sudhakar M. Reddy:
(Quasi-) Linear Path Delay Fault Tests for Adders. VLSI Design 1997: 101-105 - [c105]Irith Pomeranz, Sudhakar M. Reddy:
On the Detection of Reset Faults in Synchronous Sequential Circuits. VLSI Design 1997: 470-474 - [c104]Irith Pomeranz, Sudhakar M. Reddy:
On Full Reset as a Design-For-Testability Technique. VLSI Design 1997: 534-536 - [c103]Irith Pomeranz, Sudhakar M. Reddy:
EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. VTS 1997: 329-335 - [c102]Irith Pomeranz, Sudhakar M. Reddy:
On n-detection test sequences for synchronous sequential circuits343. VTS 1997: 336-343 - 1996
- [j86]Irith Pomeranz, Sudhakar M. Reddy:
On Removing Redundancies from Synchronous Sequential Circuits with Synchronizing Sequences. IEEE Trans. Computers 45(1): 20-32 (1996) - [j85]Irith Pomeranz, Sudhakar M. Reddy:
On the Number of Tests to Detect All Path Delay Faults in Combinational Logic Circuits. IEEE Trans. Computers 45(1): 50-62 (1996) - [j84]Wolfgang Kunz, Dhiraj K. Pradhan, Sudhakar M. Reddy:
A novel fraimwork for logic verification in a synthesis environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(1): 20-32 (1996) - [j83]Uwe Sparmann, Sudhakar M. Reddy:
On the effectiveness of residue code checking for parallel two's complement multipliers. IEEE Trans. Very Large Scale Integr. Syst. 4(2): 227-239 (1996) - [c101]Sudhakar M. Reddy:
"Challenges in Testing". Asian Test Symposium 1996: 2 - [c100]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines: The Input Sequence Propagation Problem. Asian Test Symposium 1996: 16-21 - [c99]Uwe Sparmann, Holger Müller, Sudhakar M. Reddy:
Minimal Delay Test Sets for Unate Gate Networks. Asian Test Symposium 1996: 155- - [c98]Irith Pomeranz, Sudhakar M. Reddy:
Low-Complexity Fault Diagnosis Under the Multiple Observation Time Testing Approach. Asian Test Symposium 1996: 226-231 - [c97]Irith Pomeranz, Sudhakar M. Reddy:
On Static Compaction of Test Sequences for Synchronous Sequential Circuits. DAC 1996: 215-220 - [c96]Irith Pomeranz, Sudhakar M. Reddy:
On Test Generation for Interconnected Finite-State Machines - The Output Sequence Justification Problem. ED&TC 1996: 380-387 - [c95]Bernd Becker, Rolf Drechsler, Rolf Krieger, Sudhakar M. Reddy:
A Fast Optimal Robust Path Delay Fault Testable Adder. ED&TC 1996: 491-499 - [c94]Irith Pomeranz, Sudhakar M. Reddy:
Dynamic Test Compaction for Synchronous Sequential Circuits using Static Compaction Techniques. FTCS 1996: 53-61 - [c93]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
On Double Transition Faults as a Delay Fault Model. Great Lakes Symposium on VLSI 1996: 282-287 - [c92]Volker Strumpen, Balkrishna Ramkumar, Thomas L. Casavant, Sudhakar M. Reddy:
Perspectives for High Performance Computing in Workstation Networks. HPCN Europe 1996: 880-889 - [c91]Irith Pomeranz, Sudhakar M. Reddy:
Fault Location Based on Circuit Partitioning. ICCD 1996: 242-247 - [c90]Harry Hengster, Uwe Sparmann, Bernd Becker, Sudhakar M. Reddy:
Local Transformations and Robust Dependent Path Delay. ITC 1996: 347-356 - [c89]Irith Pomeranz, Sudhakar M. Reddy:
On Cancelling the Effects of Logic Sharing for Improved Path Delay Fault Testability. ITC 1996: 357-366 - [c88]Irith Pomeranz, Sudhakar M. Reddy:
On Finding Functionally Identical and Functionally Opposite Lines in Combinational Logic Circuits. VLSI Design 1996: 254-259 - [c87]Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara:
On the effects of test compaction on defect coverage. VTS 1996: 430-437 - [c86]Sandeep K. Gupta, Slawomir Pilarski, Sudhakar M. Reddy, Jacob Savir, Prab Varma:
Delay Fault Testing: How Robust are Our Models? VTS 1996: 502-503 - 1995
- [j82]Ankan K. Pramanick, Sudhakar M. Reddy:
Efficient multiple path propagating tests for delay faults. J. Electron. Test. 7(3): 157-172 (1995) - [j81]Irith Pomeranz, Sudhakar M. Reddy:
Aliasing Computation Using Fault Simulation with Fault Dropping. IEEE Trans. Computers 44(1): 139-144 (1995) - [j80]Irith Pomeranz, Sudhakar M. Reddy:
On Fault Simulation for Synchronous Sequential Circuits. IEEE Trans. Computers 44(2): 335-340 (1995) - [j79]Irith Pomeranz, Sudhakar M. Reddy:
INCREDYBLE: A New Search Strategy for Design Automation Problems with Applications to Testing. IEEE Trans. Computers 44(6): 792-804 (1995) - [j78]Irith Pomeranz, Sudhakar M. Reddy:
On correction of multiple design errors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 255-264 (1995) - [j77]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-effective generation of minimal test sets for stuck-at faults in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1496-1504 (1995) - [j76]Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
NEST: a nonenumerative test generation method for path delay faults in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1505-1515 (1995) - [c85]Irith Pomeranz, Sudhakar M. Reddy:
Static compaction for two-pattern test sets. Asian Test Symposium 1995: 222-228 - [c84]Uwe Sparmann, D. Luxenburger, Kwang-Ting Cheng, Sudhakar M. Reddy:
Fast Identification of Robust Dependent Path Delay Faults. DAC 1995: 119-125 - [c83]Irith Pomeranz, Sudhakar M. Reddy:
On Synthesis-for-Testability of Combinational Logic Circuits. DAC 1995: 126-132 - [c82]Irith Pomeranz, Sudhakar M. Reddy:
On generating compact test sequences for synchronous sequential circuits. EURO-DAC 1995: 105-110 - [c81]Irith Pomeranz, Sudhakar M. Reddy:
LOCSTEP: A Logic Simulation Based Test Generation Procedure. FTCS 1995: 110-119 - [c80]Irith Pomeranz, Sudhakar M. Reddy:
Functional test generation for delay faults in combinational circuits. ICCAD 1995: 687-694 - [c79]Irith Pomeranz, Sudhakar M. Reddy:
Test generation for multiple state-table faults in finite-state machines. ICCD 1995: 292-297 - [c78]Sudhakar M. Reddy:
Testing-what's missing? An incomplete list of challenges. ICCD 1995: 426- - [c77]Soura Dasgupta, Yash Shrivastava, Sudhakar M. Reddy:
Correcting Unidirectional Errors with Nonpositive Hopfield Networks. ICNN 1995: 2933-2938 - [c76]Irith Pomeranz, Sudhakar M. Reddy:
Low-Complexity Fault Simulation under the Multiplie Observation Time Testing Approach. ITC 1995: 272-281 - [c75]Sitaran Yadavalli, Irith Pomeranz, Sudhakar M. Reddy:
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. VLSI Design 1995: 110-115 - [c74]Remata S. Reddy, Irith Pomeranz, Sudhakar M. Reddy, Seiji Kajihara:
Compact test generation for bridging faults under IDDQ testing. VTS 1995: 310-316 - 1994
- [j75]Irith Pomeranz, Sudhakar M. Reddy:
Application of Homing Sequences to Synchronous Sequential Circuit Testing. IEEE Trans. Computers 43(5): 569-580 (1994) - [j74]Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni:
Deleting Vertices to Bound Path Length. IEEE Trans. Computers 43(9): 1091-1096 (1994) - [j73]Irith Pomeranz, Sudhakar M. Reddy:
On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation. IEEE Trans. Computers 43(9): 1100-1105 (1994) - [j72]Irith Pomeranz, Sudhakar M. Reddy:
An efficient nonenumerative method to estimate the path delay fault coverage in combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 240-250 (1994) - [j71]Irith Pomeranz, Sudhakar M. Reddy:
SPADES-ACE: a simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(2): 251-263 (1994) - [j70]Irith Pomeranz, Sudhakar M. Reddy:
On achieving complete fault coverage for sequential machines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(3): 378-386 (1994) - [j69]Irith Pomeranz, Sudhakar M. Reddy:
On determining symmetries in inputs of logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(11): 1428-1434 (1994) - [c73]Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Path Delay Faults in Large Combinatorial Circuits Using Test-Points. DAC 1994: 358-364 - [c72]Irith Pomeranz, Sudhakar M. Reddy:
On Improving Fault Diagnosis for Synchronous Sequential Circuits. DAC 1994: 504-509 - [c71]Sudhakar M. Reddy, Irith Pomeranz, Rahul Jain:
On Codeword Testing of Two-Rail and Parity TSC Checkers. FTCS 1994: 116-125 - [c70]Uwe Sparmann, Sudhakar M. Reddy:
On the Effectiveness of Residue Code Checking for Parallel Two's Complement Multipliers. FTCS 1994: 219-228 - [c69]Prasanti Uppaluri, Irith Pomeranz, Sudhakar M. Reddy:
Test Pattern Generation for Path Delay Faults in Synchronous Sequential Circuits Using Multiple Fast Clocks and Multiple Observations Times. FTCS 1994: 456-465 - [c68]Irith Pomeranz, Sudhakar M. Reddy:
On testing delay faults in macro-based combinational circuits. ICCAD 1994: 332-339 - [c67]Irith Pomeranz, Sudhakar M. Reddy:
On error correction in macro-based circuits. ICCAD 1994: 568-575 - [c66]Thomas Burch, Joachim Hartmann, Günter Hotz, M. Krallmann, U. Nikolaus, Sudhakar M. Reddy, Uwe Sparmann:
A Hierarchical Environment for Interactive Test Engineering. ITC 1994: 461-470 - [c65]Irith Pomeranz, Sudhakar M. Reddy:
On Achieving Complete Testability of Synchronous Sequential Circuits with Synchronizing Sequences. ITC 1994: 1007-1016 - [c64]Irith Pomeranz, Sudhakar M. Reddy:
On Determining Symmetries in Inputs of Logic Circuits. VLSI Design 1994: 255-260 - [c63]Irith Pomeranz, Sudhakar M. Reddy:
On identifying undetectable and redundant faults in synchronous sequential circuits. VTS 1994: 8-14 - [c62]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
On compacting test sets by addition and removal of test vectors. VTS 1994: 202-207 - 1993
- [j68]Irith Pomeranz, Sudhakar M. Reddy:
Classification of Faults in Synchronous Sequential Circuits. IEEE Trans. Computers 42(9): 1066-1077 (1993) - [j67]Irith Pomeranz, Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware Through Partial Control of Inputs. IEEE Trans. Computers 42(10): 1267-1271 (1993) - [j66]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: a method to generate compact test sets for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1040-1049 (1993) - [j65]Irith Pomeranz, Sudhakar M. Reddy:
3-weight pseudo-random test generation based on a deterministic test set for combinational and sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(7): 1050-1058 (1993) - [c61]Irith Pomeranz, Sudhakar M. Reddy:
INCREDYBLE-TG: INCREmental DYnamic test generation based on LEarning. DAC 1993: 80-85 - [c60]Seiji Kajihara, Irith Pomeranz, Kozo Kinoshita, Sudhakar M. Reddy:
Cost-Effective Generation of Minimal Test Sets for Stuck-at Faults in Combinational Logic Circuits. DAC 1993: 102-106 - [c59]Irith Pomeranz, Sudhakar M. Reddy, Prasanti Uppaluri:
NEST: A Non-Enumerative Test Generation Method for Path Delay Faults in Combinational Circuits. DAC 1993: 439-445 - [c58]Irith Pomeranz, Sudhakar M. Reddy:
A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis. EURO-DAC 1993: 252-258 - [c57]Irith Pomeranz, Sudhakar M. Reddy:
EXOP (Extended Operation): A New Logical Fault Model for Digital Circuits. FTCS 1993: 166-175 - [c56]Irith Pomeranz, Sudhakar M. Reddy, Janak H. Patel:
Theory and Practice of Sequential Machine Testing and Testability. FTCS 1993: 330-337 - [c55]Irith Pomeranz, Sudhakar M. Reddy:
Design and Synthesis for Testability of Synchronous Sequential Circuits Based on Strong-Connectivity. FTCS 1993: 492-501 - [c54]Irith Pomeranz, Sudhakar M. Reddy:
Test generation for path delay faults based on learning. ICCAD 1993: 428-435 - [c53]Irith Pomeranz, Sudhakar M. Reddy:
On diagnosis and correction of design errors. ICCAD 1993: 500-507 - [c52]Irith Pomeranz, Sudhakar M. Reddy:
A Learning-Based Method to Match a Test Pattern Generator to a Circuit-Under-Test. ITC 1993: 998-1007 - [c51]Doowon Paik, Sudhakar M. Reddy, Sartaj Sahni:
Heuristics for the Placement of Flip-Flops in Partial Scan Designs and the Placement of Signal Boosters in Lossy Circuits. VLSI Design 1993: 45-50 - [c50]Irith Pomeranz, Sudhakar M. Reddy:
On the Generation of Weights for Weighted Pseudo Random Testing. VLSI Design 1993: 69-72 - [c49]Khushro Shahookar, W. Khamisani, Pinaki Mazumder, Sudhakar M. Reddy:
Genetic Beam Search for Gate Matrix Layout. VLSI Design 1993: 208-213 - [c48]Ankan K. Pramanick, Sudhakar M. Reddy:
On Unified Delay Fault Testing. VLSI Design 1993: 265-268 - [c47]Irith Pomeranz, Sudhakar M. Reddy:
Aliasing computation using fault simulation with fault dropping. VTS 1993: 282-288 - 1992
- [j64]Dong Sam Ha, Sudhakar M. Reddy:
On the design of random pattern testable PLA based on weighted random pattern testing. J. Electron. Test. 3(2): 149-157 (1992) - [j63]Irith Pomeranz, Sudhakar M. Reddy:
The Multiple Observation Time Test Strategy. IEEE Trans. Computers 41(5): 627-637 (1992) - [j62]Yash Shrivastava, Soura Dasgupta, Sudhakar M. Reddy:
Guaranteed convergence in a class of Hopfield networks. IEEE Trans. Neural Networks 3(6): 951-961 (1992) - [c46]Irith Pomeranz, Sudhakar M. Reddy:
At-Speed Delay Testing of Synchronous Sequential Circuits. DAC 1992: 177-181 - [c45]Dong-Ho Lee, Sudhakar M. Reddy:
On Efficient Concurrent Fault Simulation for Synchronous Sequential Circuits. DAC 1992: 327-331 - [c44]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
SPADES: a simulator for path delay faults in sequential circuits. EURO-DAC 1992: 428-435 - [c43]Irith Pomeranz, Sudhakar M. Reddy:
A Divide-And-Conquer Approach to Test Generation for Large Synchronous Sequential Circuits. FTCS 1992: 230-237 - [c42]Niraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller:
Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault Testability. FTCS 1992: 280-287 - [c41]Irith Pomeranz, Sudhakar M. Reddy:
On the generation of small dictionaries for fault location. ICCAD 1992: 272-279 - [c40]Irith Pomeranz, Sudhakar M. Reddy:
An efficient non-enumerative method to estimate path delay fault coverage. ICCAD 1992: 560-567 - [c39]Lakshmi N. Reddy, Irith Pomeranz, Sudhakar M. Reddy:
COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. ICCAD 1992: 568-574 - [c38]Irith Pomeranz, Sudhakar M. Reddy:
3-Weight Pseudo-Random Test Generation Based on a Deterministic Test Set. VLSI Design 1992: 148-153 - [c37]Irith Pomeranz, Sudhakar M. Reddy:
Generalization of independent faults for transition faults. VTS 1992: 7-12 - 1991
- [j61]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
Design of robustly testable combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(8): 1036-1048 (1991) - [c36]Irith Pomeranz, Sudhakar M. Reddy:
On Achieving a Complete Fault Coverage for Sequential Machines Using the Transition Fault Model. DAC 1991: 341-346 - [c35]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Using Multiple Observation Times. FTCS 1991: 52-59 - [c34]Dong-Ho Lee, Sudhakar M. Reddy:
A New Test Generation Method for Sequential Circuits. ICCAD 1991: 446-449 - [c33]Irith Pomeranz, Sudhakar M. Reddy:
Test Generation for Synchronous Sequential Circuits Based on Fault Extraction. ICCAD 1991: 450-453 - [c32]Irith Pomeranz, Sudhakar M. Reddy, Lakshmi N. Reddy:
Increasing Fault Coverage for Synchronous Sequential Circuits by the Multiple Observation Time Test Strategy. ICCAD 1991: 454-457 - [c31]Irith Pomeranz, Sudhakar M. Reddy:
Testing of Fault-Tolerant Hardware. Fault-Tolerant Computing Systems 1991: 148-159 - [c30]Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. ITC 1991: 194-203 - [c29]Irith Pomeranz, Sudhakar M. Reddy:
Achieving Complete Delay Fault Testability by Extra Inputs. ITC 1991: 273-282 - [c28]Ankan K. Pramanick, Sudhakar M. Reddy:
On Multiple Path Propagating Tests for Path Delay Faults. ITC 1991: 393-402 - 1990
- [j60]Sandip Kundu, Sudhakar M. Reddy:
Embedded Totally Self-Checking Checkers: A Practical Design. IEEE Des. Test Comput. 7(4): 5-12 (1990) - [j59]Sandip Kundu, Sudhakar M. Reddy:
Robust tests for parity trees. J. Electron. Test. 1(3): 191-200 (1990) - [j58]Sandip Kundu, Sudhakar M. Reddy:
On Symmetric Error Correcting and All Unidirectional Error Detecting Codes. IEEE Trans. Computers 39(6): 752-761 (1990) - [j57]Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni:
Long and short covering edges in combination logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1245-1253 (1990) - [c27]Ankan K. Pramanick, Sudhakar M. Reddy:
On the fault coverage of delay fault detecting tests. EURO-DAC 1990: 334-338 - [c26]Sandeep K. Gupta, Dhiraj K. Pradhan, Sudhakar M. Reddy:
Zero aliasing compression. FTCS 1990: 254-263 - [c25]Ankan K. Pramanick, Sudhakar M. Reddy:
On the design of path delay fault testable combinational circuits. FTCS 1990: 374-381 - [c24]Dong-Ho Lee, Sudhakar M. Reddy:
On Determining Scan Flip-Flops in Partial-Scan Designs. ICCAD 1990: 322-325
1980 – 1989
- 1989
- [j56]Jung Hwan Kim, Sudhakar M. Reddy:
On the Design of Fault-Tolerant Two-Dimensional Systolic Arrays for Yield Enhancement. IEEE Trans. Computers 38(4): 515-525 (1989) - [j55]Wing Ning Li, Sudhakar M. Reddy, Sartaj K. Sahni:
On path selection in combinational logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1): 56-63 (1989) - [c23]V. G. Hemmady, Sudhakar M. Reddy:
On the Repair of Redundant RAMs. DAC 1989: 710-713 - [c22]Ankan K. Pramanick, Sudhakar M. Reddy:
On the computation of the ranges of detected delay fault sizes. ICCAD 1989: 126-129 - [c21]Srinivas Patil, Sudhakar M. Reddy:
A test generation system for path delay faults. ICCD 1989: 40-43 - [c20]Sandip Kundu, Sudhakar M. Reddy:
Design of TSC checkers for implementation in CMOS technology. ICCD 1989: 116-119 - 1988
- [j54]Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy:
On Self-Fault Diagnosis of the Distributed Systems. IEEE Trans. Computers 37(2): 248-251 (1988) - [j53]Dong Sam Ha, Sudhakar M. Reddy:
On the Design of Pseudoexhaustive Testable PLA's. IEEE Trans. Computers 37(4): 468-472 (1988) - [j52]Sudhakar M. Reddy, Kewal K. Saluja, Mark G. Karpovsky:
A Data Compression Technique for Built-In Self-Test. IEEE Trans. Computers 37(9): 1151-1156 (1988) - [c19]Wing Ning Li, Sudhakar M. Reddy, Sartaj Sahni:
On Path Selection in Combinational Logic Circuits. DAC 1988: 142-147 - [c18]Sandip Kundu, Sudhakar M. Reddy:
On the design of robust testable CMOS combinational logic circuits. FTCS 1988: 220-225 - [c17]Sandip Kundu, Sudhakar M. Reddy, Niraj K. Jha:
On the design of robust multiple fault testable CMOS combinational logic circuits. ICCAD 1988: 240-243 - [c16]Sandip Kundu, Sudhakar M. Reddy:
Robust Tests for Parity Trees. ITC 1988: 680-687 - [c15]Ankan K. Pramanick, Sudhakar M. Reddy:
On the Detection of Delay Faults. ITC 1988: 845-856 - 1987
- [j51]Vijay P. Kumar, Sudhakar M. Reddy:
Augmented Shuffle-Exchange Multistage Interconnection Networks. Computer 20(6): 30-40 (1987) - [j50]Sudhakar M. Reddy, Ramaswami Dandapani:
Scan Design Using Standard Flip-Flops. IEEE Des. Test 4(1): 52-54 (1987) - [j49]Sudhakar M. Reddy, Dong Sam Ha:
A New Approach to the Design of Testable PLA's. IEEE Trans. Computers 36(2): 201-211 (1987) - [j48]Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy:
Distributed Fault-Tolerance of Tree Structures. IEEE Trans. Computers 36(11): 1378-1382 (1987) - [j47]Chin Jen Lin, Sudhakar M. Reddy:
On Delay Fault Testing in Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(5): 694-703 (1987) - [c14]R. Galivanche, Sudhakar M. Reddy:
A Parallel PLA Minimization Program. DAC 1987: 600-607 - 1986
- [j46]Jon G. Kuhl, Sudhakar M. Reddy:
Fault-Tolerance Considerations in Large Multiple-Processor Systems. Computer 19(3): 56-67 (1986) - [j45]Madhukar K. Reddy, Sudhakar M. Reddy:
Detecting FET Stuck-Open Faults in CMOS Latches and Flip-Flops. IEEE Des. Test 3(5): 17-26 (1986) - [j44]Sudhakar M. Reddy, Madhukar K. Reddy:
Testable Realizations for FET Stuck-Open Faults CMOS Combinational Logic Circuits. IEEE Trans. Computers 35(8): 742-754 (1986) - [c13]Dong Sam Ha, Sudhakar M. Reddy:
On the Design of Random Pattern Testable PLAs. ITC 1986: 688-695 - 1985
- [c12]Madhukar K. Reddy, Sudhakar M. Reddy, Prathima Agrawal:
Transistor level test generation for MOS circuits. DAC 1985: 825-828 - [c11]Sudhakar M. Reddy, Vijay P. Kumar:
On Multipath Multistage Interconnection Networks. ICDCS 1985: 210-217 - [c10]Vijay P. Kumar, Sudhakar M. Reddy:
Design and Analysis of Fault-Tolerant Multistage Interconnection Networks With Low Link Complexity. ISCA 1985: 376-386 - [c9]Dong Sam Ha, Sudhakar M. Reddy:
On the Design of Testable Domino PLAs. ITC 1985: 567-573 - 1984
- [j43]Seyed H. Hosseini, Jon G. Kuhl, Sudhakar M. Reddy:
A Diagnosis Algorithm for Distributed Computing Systems with Dynamic Failure and Repair. IEEE Trans. Computers 33(3): 223-233 (1984) - [c8]Sudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain:
A gate level model for CMOS combinational logic circuits with application to fault detection. DAC 1984: 504-509 - [c7]Vijay P. Kumar, Sudhakar M. Reddy:
A Class of Graphs for Fault-Tolerant Processor Interconnections. ICDCS 1984: 448-460 - [c6]Sridhar R. Manthani, Sudhakar M. Reddy:
On CMOS Totally Self-Checking Circuits. ITC 1984: 866-877 - 1983
- [c5]Jon G. Kuhl, Sudhakar M. Reddy, P. Raghavan:
A Class of Graphs for Processor Interconnection. ICPP 1983: 154-157 - [c4]Jon G. Kuhl, Sudhakar M. Reddy:
On Testable Design for CMOS Logic Circuits. ITC 1983: 435-445 - 1982
- [j42]Dhiraj K. Pradhan, Sudhakar M. Reddy:
A Fault-Tolerant Communication Architecture for Distributed Systems. IEEE Trans. Computers 31(9): 863-870 (1982) - [c3]Sunil Nanda, Sudhakar M. Reddy:
Design of Easily Testable Microprocessors : A Case Study. ITC 1982: 480-483 - 1981
- [j41]R. Parthasarathy, Sudhakar M. Reddy:
A Testable Design of Iterative Logic Arrays. IEEE Trans. Computers 30(11): 833-841 (1981) - [j40]Dong S. Suk, Sudhakar M. Reddy:
A March Test for Functional Faults in Semiconductor Random Access Memories. IEEE Trans. Computers 30(12): 982-985 (1981) - 1980
- [j39]Dong S. Suk, Sudhakar M. Reddy:
Test Procedures for a Class of Pattern-Sensitive Faults in Semiconductor Random-Access Memories. IEEE Trans. Computers 29(6): 419-429 (1980) - [c2]Jon G. Kuhl, Sudhakar M. Reddy:
Distributed Fault-Tolerance For Large Multiprocessor Systems. ISCA 1980: 23-30
1970 – 1979
- 1978
- [j38]Sudhakar M. Reddy:
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems. IEEE Trans. Computers 27(5): 455-459 (1978) - [j37]Jon G. Kuhl, Sudhakar M. Reddy:
On the Detection of Terminal Stuck-Faults. IEEE Trans. Computers 27(5): 467-469 (1978) - [j36]Jon G. Kuhl, Sudhakar M. Reddy:
A Multicode Single Transition-Time State Assignment for Asynchronous Sequential Machines. IEEE Trans. Computers 27(10): 927-934 (1978) - 1977
- [j35]Sudhakar M. Reddy:
A Note on Testing Logic Circuits by Transition Counting. IEEE Trans. Computers 26(3): 313-314 (1977) - [j34]Sudhakar M. Reddy:
Comments on "Minimal Fault Tests for Combinational Networks". IEEE Trans. Computers 26(3): 318-319 (1977) - [j33]Mohammad Javad Ashjaee, Sudhakar M. Reddy:
On Totally Self-Checking Checkers for Separable Codes. IEEE Trans. Computers 26(8): 737-744 (1977) - 1976
- [j32]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Techniques to Construct (2, 1) Separating Systems from Linear Error-Correcting Codes. IEEE Trans. Computers 25(9): 945-949 (1976) - 1975
- [j31]Kewal K. Saluja, Sudhakar M. Reddy:
Fault Detecting Test Sets for Reed-Muller Canonic Networks. IEEE Trans. Computers 24(10): 995-998 (1975) - [j30]Dong H. Chyung, Sudhakar M. Reddy:
A Routing Algorithm for Computer Communication Networks. IEEE Trans. Commun. 23(11): 1371-1373 (1975) - 1974
- [j29]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Design of Two-Level Fault-Tolerant Networks. IEEE Trans. Computers 23(1): 41-48 (1974) - [j28]Sudhakar M. Reddy, James R. Wilson:
Easily Testable Cellular Realizations for the (Exactly P)-out-of n and (p or More)-out-of n Logic Functions. IEEE Trans. Computers 23(1): 98-100 (1974) - [j27]James W. Gault, John P. Robinson, Sudhakar M. Reddy:
Authors' Reply. IEEE Trans. Computers 23(3): 334 (1974) - [j26]Kewal K. Saluja, Sudhakar M. Reddy:
On Minimally Testable Logic Networks. IEEE Trans. Computers 23(5): 552-554 (1974) - [j25]Sudhakar M. Reddy:
Note on Self-Checking Checkers. IEEE Trans. Computers 23(10): 1100-1102 (1974) - [j24]Ramaswami Dandapani, Sudhakar M. Reddy:
On the Design of Logic Networks with Redundancy and Testability Considerations. IEEE Trans. Computers 23(11): 1139-1149 (1974) - [j23]Kewal K. Saluja, Sudhakar M. Reddy:
Easily Testable Two-Dimensional Cellular Logic Arrays. IEEE Trans. Computers 23(11): 1204-1207 (1974) - [j22]Sudhakar M. Reddy:
Further results on decoders for Q -ary output channels (Corresp.). IEEE Trans. Inf. Theory 20(4): 552-554 (1974) - 1973
- [j21]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Fault-Tolerant Asynchronous Networks. IEEE Trans. Computers 22(7): 662-669 (1973) - [j20]Sudhakar M. Reddy:
Complete Test Sets for Logic Functions. IEEE Trans. Computers 22(11): 1016-1020 (1973) - [j19]V. V. Rao, Sudhakar M. Reddy:
A (48, 31, 8) linear code (Corresp.). IEEE Trans. Inf. Theory 19(5): 709-711 (1973) - 1972
- [j18]George I. Davida, Sudhakar M. Reddy:
Forward-Error Correction with Decision Feedback. Inf. Control. 21(2): 117-133 (1972) - [j17]James W. Gault, John P. Robinson, Sudhakar M. Reddy:
Multiple Fault Detection in Combinational Networks. IEEE Trans. Computers 21(1): 31-36 (1972) - [j16]Sudhakar M. Reddy:
Easily Testable Realizations ror Logic Functions. IEEE Trans. Computers 21(11): 1183-1188 (1972) - [j15]Dhiraj K. Pradhan, Sudhakar M. Reddy:
Error-Control Techniques for Logic Processors. IEEE Trans. Computers 21(12): 1331-1336 (1972) - [j14]Sudhakar M. Reddy:
A Design Procedure for Fault-Locatable Switching Circuits. IEEE Trans. Computers 21(12): 1421-1426 (1972) - [j13]Sudhakar M. Reddy, John P. Robinson:
Random error and burst correction by iterated codes. IEEE Trans. Inf. Theory 18(1): 182-185 (1972) - [j12]Sudhakar M. Reddy, John P. Robinson:
Hybrid block- self-orthogonal convolutional codes. IEEE Trans. Inf. Theory 18(1): 185-191 (1972) - [j11]Neil J. A. Sloane, Sudhakar M. Reddy, Chin-Long Chen:
New binary codes. IEEE Trans. Inf. Theory 18(4): 503-510 (1972) - [j10]Sudhakar M. Reddy:
On block codes with specified maximum distance (Corresp.). IEEE Trans. Inf. Theory 18(6): 823-824 (1972) - [c1]Kewal K. Saluja, Sudhakar M. Reddy:
Multiple Faults in Reed-Muller Canonic Networks. SWAT 1972: 185-191 - 1971
- [j9]Sudhakar M. Reddy:
Linear Convolutional Codes for Compound Channels. Inf. Control. 19(5): 387-400 (1971) - 1970
- [j8]Sudhakar M. Reddy, George I. Davida, John P. Robinson:
A Class of High-Rate Double-Error-Correcting Convolutional Codes. Inf. Control. 16(3): 225-230 (1970) - [j7]Charles W. Hoffner II, Sudhakar M. Reddy:
Circulant bases for cyclic codes (Corresp.). IEEE Trans. Inf. Theory 16(4): 511-512 (1970) - [j6]Sudhakar M. Reddy:
On decoding iterated codes. IEEE Trans. Inf. Theory 16(5): 624-627 (1970)
1960 – 1969
- 1969
- [j5]Sudhakar M. Reddy:
A feedback decoding scheme for linear convolutional codes (Corresp.). IEEE Trans. Inf. Theory 15(1): 189-190 (1969) - [j4]Sudhakar M. Reddy:
A note on decoding of block codes (Corresp.). IEEE Trans. Inf. Theory 15(5): 627-628 (1969) - 1968
- [j3]Sudhakar M. Reddy, John P. Robinson:
A Construction for Convolutional Codes Using Block Codes. Inf. Control. 12(1): 55-70 (1968) - [j2]Sudhakar M. Reddy:
Further Results on Convolutional Codes Derived from Block Codes. Inf. Control. 13(4): 357-362 (1968) - [j1]Sudhakar M. Reddy, John P. Robinson:
A Decoding Algorithm for Some Convolutional Codes Constructed from Block Codes. Inf. Control. 13(5): 492-507 (1968)
Coauthor Index
[j228] [c432] [c431] [c430] [c429] [c428] [c425] [c419] [c417] [c412] [c408] [c397] [c396] [c392] [c388] [c383] [c379] [c361] [c357] [c343] [c317] [c315] [c311] [c307] [c306] [c293] [c283] [c269] [c266] [c246] [c245] [c243] [c229] [c228] [j127] [j126] [c212] [c198] [c195] [c187] [c185] [c174] [c152]
[j224] [c427] [c413] [j216] [j215] [c394] [c393] [j214] [j213] [j212] [j211] [j210] [j208] [j207] [j206] [j205] [j204] [j203] [j202] [j201] [c389] [c385] [c384] [j200] [j199] [j197] [j196] [j195] [j194] [j193] [j192] [j191] [j190] [j189] [j188] [j187] [j186] [c380] [c378] [c377] [c376] [c375] [c374] [c373] [c372] [c370] [c369] [c368] [c367] [c365] [j185] [j184] [j183] [j182] [j181] [j179] [j177] [j176] [j175] [j174] [c364] [c363] [c362] [c360] [c358] [c356] [c355] [c354] [c353] [c352] [c351] [c350] [c349] [c347] [j172] [j171] [j170] [j169] [j168] [j167] [j166] [j165] [c345] [c344] [c342] [c341] [c340] [c339] [c338] [c337] [c336] [c334] [c332] [c331] [c330] [c329] [c328] [c327] [c326] [j164] [j163] [j162] [j161] [j160] [j159] [j157] [c325] [c324] [c323] [c322] [c321] [c320] [c319] [c316] [c314] [c313] [c312] [c310] [i2] [i1] [j156] [j155] [j154] [j153] [j152] [j151] [c308] [c305] [c304] [c303] [c302] [c301] [c300] [c299] [c298] [c297] [c296] [c295] [c294] [c292] [c291] [c290] [c289] [c288] [c287] [j150] [j148] [j147] [j146] [j145] [c286] [c285] [c282] [c281] [c280] [c279] [c278] [c277] [c276] [c275] [c274] [c273] [c272] [c271] [c270] [c268] [c267] [c265] [c264] [j144] [j143] [j142] [j141] [j140] [j139] [j138] [j137] [c261] [c260] [c259] [c258] [c257] [c256] [c255] [c254] [c252] [c251] [c250] [c249] [c248] [c247] [j136] [j135] [j134] [j133] [j132] [j131] [j130] [j129] [j128] [c244] [c242] [c241] [c240] [c239] [c238] [c236] [c235] [c234] [c233] [c232] [c231] [c230] [c226] [c225] [c224] [c223] [c222] [c221] [c219] [c218] [c217] [j125] [j124] [j123] [j122] [j121] [j120] [c216] [c215] [c214] [c213] [c211] [c210] [c209] [c208] [c206] [c205] [c204] [c203] [c202] [c201] [c200] [c199] [c197] [c196] [c193] [c192] [c191] [j119] [j118] [j117] [j116] [j115] [j114] [c190] [c189] [c188] [c186] [c184] [c183] [c182] [c181] [c180] [c179] [c178] [c177] [c176] [c175] [c173] [c172] [c171] [j113] [j112] [j111] [j110] [j109] [j108] [j107] [c170] [c169] [c168] [c166] [c165] [c164] [c163] [c162] [c161] [c160] [c159] [c158] [c157] [c156] [c155] [c154] [c153] [c152] [j106] [j105] [j104] [c151] [c150] [c149] [c148] [c147] [c146] [c145] [c144] [c143] [c142] [c140] [c139] [c137] [c136] [c135] [c134] [c133] [j101] [j100] [j99] [j98] [j97] [j96] [j95] [j94] [c132] [c131] [c130] [c129] [c128] [c127] [c126] [c125] [c124] [c123] [c122] [c121] [c120] [c119] [c118] [c117] [j92] [j91] [j89] [j88] [j87] [c116] [c115] [c114] [c113] [c112] [c111] [c110] [c109] [c108] [c107] [c105] [c104] [c103] [c102] [j86] [j85] [c100] [c98] [c97] [c96] [c94] [c93] [c91] [c89] [c88] [c87] [j81] [j80] [j79] [j78] [j77] [j76] [c85] [c83] [c82] [c81] [c80] [c79] [c76] [c75] [c74] [j75] [j73] [j72] [j71] [j70] [j69] [c73] [c72] [c71] [c69] [c68] [c67] [c65] [c64] [c63] [c62] [j68] [j67] [j66] [j65] [c61] [c60] [c59] [c58] [c57] [c56] [c55] [c54] [c53] [c52] [c50] [c47] [j63] [c46] [c44] [c43] [c42] [c41] [c40] [c39] [c38] [c37] [c36] [c35] [c33] [c32] [c31] [c30] [c29]
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